219 lines
6.2 KiB
C
219 lines
6.2 KiB
C
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
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/*
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* EXAMPLE OUTPUT
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*
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* ---------------------------------------------------------------------
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*
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* tt = 0x02, illegal_instruction
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*
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* INS LOCALS OUTS GLOBALS
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* 0: 00000000 f3900fc0 40007c50 00000000
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* 1: 00000000 40004bf0 40008d30 40008c00
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* 2: 00000000 40004bf4 40008000 00000003
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* 3: 40009158 00000000 40009000 00000002
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* 4: 40008fa8 40003c00 40008fa8 00000008
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* 5: 40009000 f3400fc0 00000000 00000080
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* 6: 4000a1f8 40000050 4000a190 00000000
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* 7: 40002308 00000000 40001fb8 000000c1
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*
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* psr: f30000c7 wim: 00000008 tbr: 40000020 y: 00000000
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* pc: 4000a1f4 npc: 4000a1f8
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*
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* pc sp
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* #0 4000a1f4 4000a190
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* #1 40002308 4000a1f8
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* #2 40003b24 4000a258
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*
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* ---------------------------------------------------------------------
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*
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*
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* INTERPRETATION
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*
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* INS, LOCALS, OUTS and GLOBALS represent the %i, %l, %o and %g
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* registers before the trap was taken.
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*
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* wim, y, pc and npc are the values before the trap was taken.
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* tbr has the tbr.tt field (bits 11..4) filled in by hardware
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* representing the current trap type. psr is read immediately
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* after the trap was taken so it will have the new CWP and ET=0.
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*
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* The "#i pc sp" rows is the stack backtrace. All register
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* windows are flushed to the stack prior to printing. First row
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* is the trapping pc and sp (o6).
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*
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*
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* HOW TO USE
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*
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* When invesetigating a crashed program, the first things to look
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* at is typically the tt, pc and sp (o6). You can lookup the pc
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* in the assembly list file or use addr2line. In the listing, the
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* register values in the table above can be used. The linker map
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* file will give a hint on which stack is active and if it has
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* overflowed.
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*
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* psr bits 11..8 is the processor interrupt (priority) level. 0
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* is lowest priority level (all can be taken), and 0xf is the
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* highest level where only non-maskable interrupts are taken.
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*
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* g0 is always zero. g5, g6 are never accessed by the compiler.
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* g7 is the TLS pointer if enabled. A SAVE instruction decreases
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* the current window pointer (psr bits 4..0) which results in %o
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* registers becoming %i registers and a new set of %l registers
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* appear. RESTORE does the oppposite.
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*/
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/*
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* The SPARC V8 ABI guarantees that the stack pointer register
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* (o6) points to an area organized as "struct savearea" below at
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* all times when traps are enabled. This is the register save
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* area where register window registers can be flushed to the
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* stack.
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*
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* We flushed registers to this space in the fault trap entry
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* handler. Note that the space is allocated by the ABI (compiler)
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* for each stack frame.
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*
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* When printing the registers, we get the "local" and "in"
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* registers from the ABI stack save area, while the "out" and
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* "global" registares are taken from the exception stack frame
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* generated in the fault trap entry.
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*/
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struct savearea {
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uint32_t local[8];
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uint32_t in[8];
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};
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/*
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* Exception trap type (tt) values according to The SPARC V8
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* manual, Table 7-1.
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*/
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static const struct {
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int tt;
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const char *desc;
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} TTDESC[] = {
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{ .tt = 0x02, .desc = "illegal_instruction", },
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{ .tt = 0x07, .desc = "mem_address_not_aligned", },
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{ .tt = 0x2B, .desc = "data_store_error", },
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{ .tt = 0x29, .desc = "data_access_error", },
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{ .tt = 0x09, .desc = "data_access_exception", },
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{ .tt = 0x21, .desc = "instruction_access_error", },
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{ .tt = 0x01, .desc = "instruction_access_exception", },
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{ .tt = 0x04, .desc = "fp_disabled", },
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{ .tt = 0x08, .desc = "fp_exception", },
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{ .tt = 0x2A, .desc = "division_by_zero", },
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{ .tt = 0x03, .desc = "privileged_instruction", },
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{ .tt = 0x20, .desc = "r_register_access_error", },
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{ .tt = 0x0B, .desc = "watchpoint_detected", },
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{ .tt = 0x2C, .desc = "data_access_MMU_miss", },
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{ .tt = 0x3C, .desc = "instruction_access_MMU_miss", },
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{ .tt = 0x05, .desc = "window_overflow", },
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{ .tt = 0x06, .desc = "window_underflow", },
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{ .tt = 0x0A, .desc = "tag_overflow", },
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};
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static void print_trap_type(const z_arch_esf_t *esf)
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{
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const int tt = (esf->tbr & TBR_TT) >> TBR_TT_BIT;
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const char *desc = "unknown";
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if (tt & 0x80) {
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desc = "trap_instruction";
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} else if (tt >= 0x11 && tt <= 0x1F) {
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desc = "interrupt";
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} else {
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for (int i = 0; i < ARRAY_SIZE(TTDESC); i++) {
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if (TTDESC[i].tt == tt) {
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desc = TTDESC[i].desc;
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break;
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}
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}
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}
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LOG_ERR("tt = 0x%02X, %s", tt, desc);
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}
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static void print_integer_registers(const z_arch_esf_t *esf)
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{
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const struct savearea *flushed = (struct savearea *) esf->out[6];
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LOG_ERR(" INS LOCALS OUTS GLOBALS");
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for (int i = 0; i < 8; i++) {
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LOG_ERR(
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" %d: %08x %08x %08x %08x",
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i,
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flushed ? flushed->in[i] : 0,
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flushed ? flushed->local[i] : 0,
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esf->out[i],
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esf->global[i]
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);
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}
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}
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static void print_special_registers(const z_arch_esf_t *esf)
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{
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LOG_ERR(
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"psr: %08x wim: %08x tbr: %08x y: %08x",
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esf->psr, esf->wim, esf->tbr, esf->y
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);
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LOG_ERR(" pc: %08x npc: %08x", esf->pc, esf->npc);
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}
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static void print_backtrace(const z_arch_esf_t *esf)
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{
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const int MAX_LOGLINES = 40;
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const struct savearea *s = (struct savearea *) esf->out[6];
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LOG_ERR(" pc sp");
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LOG_ERR(" #0 %08x %08x", esf->pc, (unsigned int) s);
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for (int i = 1; s && i < MAX_LOGLINES; i++) {
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const uint32_t pc = s->in[7];
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const uint32_t sp = s->in[6];
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if (sp == 0U && pc == 0U) {
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break;
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}
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LOG_ERR(" #%-2d %08x %08x", i, pc, sp);
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if (sp == 0U || sp & 7U) {
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break;
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}
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s = (const struct savearea *) sp;
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}
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}
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static void print_all(const z_arch_esf_t *esf)
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{
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LOG_ERR("");
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print_trap_type(esf);
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LOG_ERR("");
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print_integer_registers(esf);
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LOG_ERR("");
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print_special_registers(esf);
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LOG_ERR("");
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print_backtrace(esf);
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LOG_ERR("");
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}
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FUNC_NORETURN void z_sparc_fatal_error(unsigned int reason,
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const z_arch_esf_t *esf)
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{
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if (esf != NULL) {
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if (IS_ENABLED(CONFIG_EXTRA_EXCEPTION_INFO)) {
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print_all(esf);
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} else {
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print_special_registers(esf);
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}
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}
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z_fatal_error(reason, esf);
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CODE_UNREACHABLE;
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}
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