156 lines
3.6 KiB
ArmAsm
156 lines
3.6 KiB
ArmAsm
/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "asm_memory_management.h"
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.section .text, "ax"
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.align 64
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power_down_literals:
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.literal_position
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ipc_flag:
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.word 0x80000000 // IPC_DIPCTDR_BUSY
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sram_dis_loop_cnt:
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.word 4096
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.global power_down
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.type power_down, @function
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/**
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* @brief Perform power down.
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*
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* Depending on arguments, memories are switched off.
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*
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* @param A2 - argument for LPSRAM
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* @param A3 - pointer to array containing power gating mask.
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* Size of array is determined by MAX_MEMORY_SEGMENTS define.
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* @param A4 - send response to ipc
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*/
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#define IPC_HOST_BASE 0x00073000
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#define b_enable_lpsram a2
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#define pu32_hpsram_mask a3
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#define b_ipc_response a4
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#define temp_reg0 a6
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#define temp_reg1 a7
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#define temp_reg2 a8
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#define temp_reg3 a9
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#define temp_reg4 a10
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#define temp_reg5 a11
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#define temp_reg6 a12
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#define p_ipc_regs a13
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#define u32_ipc_response_mask a14
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#define pfl_reg a15
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power_down:
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entry sp, 32
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/**
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* effectively executes:
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* xthal_dcache_region_lock(&literals, 128);
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* xthal_dcache_region_lock(&powerdown, 256);
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* xthal_dcache_region_lock(&pu32_hpsram_mask, 64);
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*/
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movi pfl_reg, power_down_literals
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dpfl pfl_reg, 0
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dpfl pfl_reg, 64
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movi pfl_reg, power_down
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ipfl pfl_reg, 0
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ipfl pfl_reg, 64
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ipfl pfl_reg, 128
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ipfl pfl_reg, 192
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mov pfl_reg, pu32_hpsram_mask
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dpfl pfl_reg, 0
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/* move some values to registries before switching off whole memory */
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/* load address of DIPCTDR register */
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movi p_ipc_regs, IPC_HOST_BASE
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movi u32_ipc_response_mask, 0x20000000
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_PD_DISABLE_LPSRAM:
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/**
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* effectively executes:
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* if (b_enable_lpsram) {
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* ace_lpsram_power_down_entire();
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* }
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*/
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beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
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m_ace_lpsram_power_down_entire temp_reg0, temp_reg1, temp_reg2, temp_reg3
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_PD_DISABLE_HPSRAM:
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/* if value in memory pointed by pu32_hpsram_mask = 0
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(hpsram_pwrgating_mask) - do not disable hpsram. */
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beqz pu32_hpsram_mask, _PD_SEND_IPC
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/**
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* effectively executes:
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* for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0;
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* --seg_index) {
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* ace_hpsram_power_change(seg_index, mask[seg_index]);
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* }
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* where mask is given in pu32_hpsram_mask register
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*/
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.set seg_index, MAX_MEMORY_SEGMENTS - 1
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.rept MAX_MEMORY_SEGMENTS
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l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index
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m_ace_hpsram_power_change\
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/*segment_index=*/ seg_index,\
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/*mask=*/ temp_reg0,\
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temp_reg1,\
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temp_reg2,\
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temp_reg3,\
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temp_reg4,\
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temp_reg5
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.set seg_index, seg_index - 1
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.endr
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_PD_SEND_IPC:
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/**
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* Send IPC to host informing of PD completion - Clear BUSY
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* bit by writing IPC_DIPCTDR_BUSY to IPC_DIPCTDR
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* and writing IPC_DIPCTDA_DONE to IPC_DIPCTDA
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*/
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/**
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* effecfively executes:
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* if (b_ipc_response)
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* {
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* temp_reg0 = *p_ipc_regs;
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* temp_reg0 = temp_reg0 | 0x80000000;
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* temp_reg0 = temp_reg0 | u32_ipc_response_mask;
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* *(p_ipc_regs + 0x180) = 0x0;
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* *(p_ipc_regs + 0x10) = temp_reg0;
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* }
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*/
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beqz b_ipc_response, _PD_SLEEP
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/* copy value from IPCxTDR */
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l32i temp_reg0, p_ipc_regs, 0
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/* set IPC Busy bit to 1 */
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movi temp_reg1, 1
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slli temp_reg1, temp_reg1, 31
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or temp_reg0, temp_reg0, temp_reg1
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/* mark the message as a reply */
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or temp_reg0, temp_reg0, u32_ipc_response_mask
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/* clear IPCxIDD i.e. message extension */
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movi temp_reg1, 0
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s32i temp_reg1, p_ipc_regs, 0x180
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/* write response to IPCxIDR */
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s32i temp_reg0, p_ipc_regs, 0x10
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_PD_SLEEP:
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/* effecfively executes:
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* xmp_spin()
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* waiti 5
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*/
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movi temp_reg0, 128
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loop:
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addi temp_reg0, temp_reg0, -1
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bnez temp_reg0, loop
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extw
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extw
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waiti 5
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1:
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j 1b
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.size power_down , . - power_down
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