494 lines
13 KiB
Plaintext
494 lines
13 KiB
Plaintext
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the intel_apl_adsp platform
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*/
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OUTPUT_ARCH(xtensa)
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#include <zephyr/devicetree.h>
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#include <xtensa/config/core-isa.h>
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#include <zephyr/linker/sections.h>
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#include <adsp-vectors.h>
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#include <adsp_memory.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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ENTRY(rom_entry);
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/* DSP RAM regions (all of them) are mapped twice on the DSP. One
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* mapping is set up to bypass the L1 cache, so it must be used when
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* multiprocessor coherence is desired, where the latter mapping is
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* best used for processor-local data (e.g. stacks) or shared data
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* that is managed with explicit cache flush/invalidate operations.
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*
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* These macros will set up a segment start address correctly,
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* including alignment to a cache line. Be sure to also emit the
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* section to ">ram" or ">ucram" as appropriate, to prevent the linker
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* from filling in 512MB of sparse zeros.
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*/
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#ifdef CONFIG_KERNEL_COHERENCE
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#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))
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#define SEGSTART_CACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)
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#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)
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#else
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#define SEGSTART_CACHED .
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#define SEGSTART_UNCACHED .
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#define ucram ram
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#endif
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/* intlist.ld needs an IDT_LIST memory region */
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#define IDT_BASE 0xe0000000
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#define IDT_SIZE 0x2000
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/* rimage module sections are C struct data, and thus flagged ALLOC.
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* The xcc linker demands they be in a declared memory region even if
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* the enclosing output section is (NOLOAD). Put them here.
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*/
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#define NOLOAD_BASE 0x20000
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#define NOLOAD_SIZE 0x100000
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MEMORY {
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vector_base_text :
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org = VECBASE_RESET_PADDR_SRAM,
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len = MEM_VECBASE_LIT_SIZE
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vector_int2_lit :
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org = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int2_text :
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org = INTLEVEL2_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int3_lit :
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org = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int3_text :
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org = INTLEVEL3_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int4_lit :
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org = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int4_text :
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org = INTLEVEL4_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int7_lit :
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org = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int7_text :
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org = INTLEVEL7_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_kernel_lit :
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org = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_kernel_text :
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org = KERNEL_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_user_lit :
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org = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_user_text :
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org = USER_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_double_lit :
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org = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_double_text :
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org = DOUBLEEXC_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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imr :
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org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
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len = 0x100000
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ram :
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org = RAM_BASE,
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len = RAM_SIZE
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#ifdef CONFIG_KERNEL_COHERENCE
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ucram :
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org = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),
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len = RAM_SIZE
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#endif
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST :
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org = IDT_BASE,
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len = IDT_SIZE
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#endif
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lpram :
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org = LP_SRAM_BASE,
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len = LP_SRAM_SIZE
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noload :
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org = NOLOAD_BASE,
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len = NOLOAD_SIZE
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}
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SECTIONS {
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/* Boot loader code in IMR memory */
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.imr : {
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_imr_start = .;
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/* Entry point MUST be here per external configuration */
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KEEP (*(.boot_entry.text))
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*(.imr .imr.*)
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} >imr
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/* Boot loader data. Note that rimage seems to want this
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* page-aligned or it will throw an error, not sure why since all
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* the ROM cares about is a contiguous region. And it's
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* particularly infuriating as it precludes linker .rodata next to
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* .text.
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*/
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.imrdata : ALIGN(4096) {
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*(.imrdata .imrdata.*)
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_imr_end = .;
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} >imr
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.WindowVectors.text : {
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_WindowVectors_text_start = .;
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KEEP (*(.WindowVectors.text))
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_WindowVectors_text_end = .;
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} >vector_base_text
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.Level2InterruptVector.literal : {
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_Level2InterruptVector_literal_start = .;
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*(.Level2InterruptVector.literal)
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_Level2InterruptVector_literal_end = .;
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} >vector_int2_lit
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.Level2InterruptVector.text : {
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_Level2InterruptVector_text_start = .;
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KEEP (*(.Level2InterruptVector.text))
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_Level2InterruptVector_text_end = .;
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} >vector_int2_text
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.Level3InterruptVector.literal : {
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_Level3InterruptVector_literal_start = .;
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*(.Level3InterruptVector.literal)
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_Level3InterruptVector_literal_end = .;
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} >vector_int3_lit
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.Level3InterruptVector.text : {
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_Level3InterruptVector_text_start = .;
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KEEP (*(.Level3InterruptVector.text))
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_Level3InterruptVector_text_end = .;
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} >vector_int3_text
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.Level4InterruptVector.literal : {
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_Level4InterruptVector_literal_start = .;
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*(.Level4InterruptVector.literal)
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_Level4InterruptVector_literal_end = .;
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} >vector_int4_lit
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.Level4InterruptVector.text : {
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_Level4InterruptVector_text_start = .;
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KEEP (*(.Level4InterruptVector.text))
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_Level4InterruptVector_text_end = .;
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} >vector_int4_text
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.DebugExceptionVector.literal : {
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_DebugExceptionVector_literal_start = .;
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*(.DebugExceptionVector.literal)
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_DebugExceptionVector_literal_end = .;
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} >vector_int4_lit
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.DebugExceptionVector.text : {
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_DebugExceptionVector_text_start = .;
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KEEP (*(.DebugExceptionVector.text))
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_DebugExceptionVector_text_end = .;
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} >vector_int4_text
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.NMIExceptionVector.literal : {
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_NMIExceptionVector_literal_start = .;
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*(.NMIExceptionVector.literal)
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_NMIExceptionVector_literal_end = .;
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} >vector_int7_lit
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.NMIExceptionVector.text : {
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_NMIExceptionVector_text_start = .;
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KEEP (*(.NMIExceptionVector.text))
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_NMIExceptionVector_text_end = .;
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} >vector_int7_text
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.KernelExceptionVector.literal : {
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_KernelExceptionVector_literal_start = .;
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*(.KernelExceptionVector.literal)
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_KernelExceptionVector_literal_end = .;
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} >vector_kernel_lit
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.KernelExceptionVector.text : {
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_KernelExceptionVector_text_start = .;
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KEEP (*(.KernelExceptionVector.text))
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_KernelExceptionVector_text_end = .;
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} >vector_kernel_text
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.UserExceptionVector.literal : {
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_UserExceptionVector_literal_start = .;
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*(.UserExceptionVector.literal)
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_UserExceptionVector_literal_end = .;
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} >vector_user_lit
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.UserExceptionVector.text : {
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_UserExceptionVector_text_start = .;
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KEEP (*(.UserExceptionVector.text))
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_UserExceptionVector_text_end = .;
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} >vector_user_text
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.DoubleExceptionVector.literal : {
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_DoubleExceptionVector_literal_start = .;
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*(.DoubleExceptionVector.literal)
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_DoubleExceptionVector_literal_end = .;
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} >vector_double_lit
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.DoubleExceptionVector.text : {
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_DoubleExceptionVector_text_start = .;
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KEEP (*(.DoubleExceptionVector.text))
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_DoubleExceptionVector_text_end = .;
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} >vector_double_text
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.text : {
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__text_region_start = .;
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*(.iram1 .iram1.*)
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*(.entry.text)
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*(.init.literal)
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*(.iram0.text)
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KEEP(*(.init))
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KEEP(*(.lps_vector))
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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KEEP(*(.fini))
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*(.gnu.version)
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__text_region_end = .;
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} >ram
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.rodata : ALIGN(4096)
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{
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__rodata_region_start = .;
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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. = ALIGN(4);
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#include <snippets-rodata.ld>
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__XT_EXCEPTION_TABLE__ = .;
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KEEP (*(.xt_except_table))
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KEEP (*(.gcc_except_table .gcc_except_table.*))
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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KEEP (*(.eh_frame))
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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__XT_EXCEPTION_DESCS__ = .;
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = .;
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_image_ram_start = .;
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_bss_table_start = .;
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LONG(_bss_start)
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LONG(_bss_end)
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_bss_table_end = .;
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} >ram
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.module_init : {
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_module_init_start = .;
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*(*.initcall)
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_module_init_end = .;
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} >ram
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#define RAMABLE_REGION ram
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#define ROMABLE_REGION ram
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#include <zephyr/linker/common-rom.ld>
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__rodata_region_end = .;
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.fw_ready : {
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KEEP(*(".fw_ready"));
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KEEP (*(.fw_ready_metadata))
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} >ram
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.noinit SEGSTART_UNCACHED : {
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*(.noinit)
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*(.noinit.*)
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} >ucram
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.data SEGSTART_UNCACHED : {
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__data_start = .;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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KEEP(*(.gnu.linkonce.d.*personality*))
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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KEEP(*(.jcr))
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_trace_ctx_start = ABSOLUTE(.);
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*(.trace_ctx)
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_trace_ctx_end = ABSOLUTE(.);
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*(.gna_model)
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__data_end = .;
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} >ucram
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.lit4 SEGSTART_CACHED : {
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_lit4_start = .;
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = .;
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} >ram
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/* These values need to change in our scheme, where the common-ram
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* sections need to be linked in safe/uncached memory but common-rom
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* wants to use the cache
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*/
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. = SEGSTART_UNCACHED;
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#undef RAMABLE_REGION
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#undef ROMABLE_REGION
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#define RAMABLE_REGION ucram
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#define ROMABLE_REGION ucram
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#include <zephyr/linker/common-ram.ld>
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.tm_clone_table : {
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*(.tm_clone_table)
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} >ram
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/* This section is cached. By default it contains only declared
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* thread stacks, but applications can put symbols here too.
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*/
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.cached SEGSTART_CACHED : {
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_cached_start = .;
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*(.cached .cached.*)
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_cached_end = .;
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} >ram
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/* Rimage requires 4k alignment between "DATA" and "BSS", can't do
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* this in the section declaration below because we're also changing
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* cacheability and that leaves a gap in the image large enough for
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* binutils to decide to warn about (no way to turn that off, it
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* seems, --warn-section-align is on by default)
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*/
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. = ALIGN(4096);
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.bss SEGSTART_UNCACHED (NOLOAD) :
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{
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_bss_start = .;
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(8);
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_bss_end = .;
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} >ucram
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. = SEGSTART_UNCACHED;
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_end = ALIGN(8);
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/* Heap start and end markers. Used to reserve system heap memory. */
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.heap_mem SEGSTART_UNCACHED (NOLOAD) :
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{
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_heap_start = .;
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*(.heap_mem)
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} >ucram
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.unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :
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{
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. = ALIGN(4096);
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_unused_ram_start_marker = .;
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*(.unused_ram_start_marker)
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*(.unused_ram_start_marker.*)
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z_mapped_end = .;
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} >ram
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|
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/* Heap start and end markers. Used with libc malloc code. */
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. = SEGSTART_UNCACHED;
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_end = ALIGN(8);
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. = SEGSTART_CACHED;
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. = L2_SRAM_BASE + L2_SRAM_SIZE;
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. = SEGSTART_UNCACHED;
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_heap_end = .;
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_heap_sentry = .;
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|
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/* dma buffers */
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.lpbuf (NOLOAD): {
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_dma_buf_start = .;
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*(.dma_buffers)
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_dma_buf_end = .;
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_image_ram_end = .;
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} >lpram
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|
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/* Non-loadable sections below. Back to cached memory so
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* the cache remap script doesn't try to move them around needlessly.
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*/
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. = SEGSTART_CACHED;
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|
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/* rimage module manifest headers */
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.module.boot : { KEEP(*(.module.boot)) } >noload
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.module.main : { KEEP(*(.module.main)) } >noload
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|
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.static_uuid_entries : {
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*(*.static_uuids)
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} >noload
|
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|
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.static_log_entries : {
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*(*.static_log*)
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} >noload
|
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|
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/* This is the "extended manifest" data (mostly versioning stuff)
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* emitted by SOF and inspected by the kernel driver. It doesn't
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* appear directly in the image, but rimage will parse and repack
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* this into the output file header, so requires this be present
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* even if empty. Alignment and padding to 16 bytes is required,
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* otherwise rimage will complain about the size being wrong (which
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* sounds like a struct should be declared packed somewhere...)
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*/
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.fw_metadata : ALIGN(16) {
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KEEP (*(.fw_metadata))
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. = ALIGN(16);
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} >noload
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#include <snippets-sections.ld>
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#include <zephyr/linker/debug-sections.ld>
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/DISCARD/ : { *(.note.GNU-stack) }
|
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.xtensa.info 0 : { *(.xtensa.info) }
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|
.xt.insn 0 : {
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KEEP (*(.xt.insn))
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|
KEEP (*(.gnu.linkonce.x.*))
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}
|
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.xt.prop 0 : {
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|
KEEP (*(.xt.prop))
|
|
KEEP (*(.xt.prop.*))
|
|
KEEP (*(.gnu.linkonce.prop.*))
|
|
}
|
|
.xt.lit 0 : {
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|
KEEP (*(.xt.lit))
|
|
KEEP (*(.xt.lit.*))
|
|
KEEP (*(.gnu.linkonce.p.*))
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|
}
|
|
.xt.profile_range 0 : {
|
|
KEEP (*(.xt.profile_range))
|
|
KEEP (*(.gnu.linkonce.profile_range.*))
|
|
}
|
|
.xt.profile_ranges 0 : {
|
|
KEEP (*(.xt.profile_ranges))
|
|
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
|
}
|
|
.xt.profile_files 0 : {
|
|
KEEP (*(.xt.profile_files))
|
|
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
|
}
|
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|
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <zephyr/linker/intlist.ld>
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#endif
|
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}
|