191 lines
4.9 KiB
C
191 lines
4.9 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for nxp_lpc54114 platform
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*
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* This module provides routines to initialize and support board-level
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* hardware for the nxp_lpc54114 platform.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/cpu.h>
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#include <cortex_m/exc.h>
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#include <fsl_power.h>
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#include <fsl_clock.h>
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#include <fsl_common.h>
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#include <fsl_device_registers.h>
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#ifdef CONFIG_GPIO_MCUX_LPC
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#include <fsl_pint.h>
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#endif
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#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
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#include <zephyr_image_info.h>
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/* Memcpy macro to copy segments from secondary core image stored in flash
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* to RAM section that secondary core boots from.
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* n is the segment number, as defined in zephyr_image_info.h
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*/
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#define MEMCPY_SEGMENT(n, _) \
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memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \
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(uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \
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(SEGMENT_SIZE_ ## n))
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#endif
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/**
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*
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* @brief Initialize the system clock
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*
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*/
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#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
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static ALWAYS_INLINE void clock_init(void)
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{
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#ifdef CONFIG_SOC_LPC54114_M4
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/* Set up the clock sources */
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/* Ensure FRO is on */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
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/*
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* Switch to FRO 12MHz first to ensure we can change voltage without
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* accidentally being below the voltage for current speed.
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*/
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
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/* Set FLASH wait states for core */
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CLOCK_SetFLASHAccessCyclesForFreq(CPU_FREQ);
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/* Set up high frequency FRO output to selected frequency */
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CLOCK_SetupFROClocking(CPU_FREQ);
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/* Set up dividers */
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/* Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
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/* Set up clock selectors - Attach clocks to the peripheries */
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/* Switch MAIN_CLK to FRO_HF */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
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/* Attach 12 MHz clock to FLEXCOMM0 */
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
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/* attach 12 MHz clock to FLEXCOMM4 */
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
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/* reset FLEXCOMM for I2C */
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RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay)
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/* Attach 12 MHz clock to FLEXCOMM5 */
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CLOCK_AttachClk(kFRO_HF_to_FLEXCOMM5);
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/* reset FLEXCOMM for SPI */
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RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
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#endif
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#endif /* CONFIG_SOC_LPC54114_M4 */
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int nxp_lpc54114_init(void)
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{
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/* Initialize FRO/system clock to 48 MHz */
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clock_init();
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#ifdef CONFIG_GPIO_MCUX_LPC
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/* Turn on PINT device*/
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PINT_Init(PINT);
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#endif
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return 0;
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}
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SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
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#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M0)
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/* M4 core has a custom platform initialization routine in assembly,
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* but M0 core does not. install one here to call SystemInit.
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*/
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void z_arm_platform_init(void)
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{
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SystemInit();
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}
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#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
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#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
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#define CORE_M0_BOOT_ADDRESS ((void *)CONFIG_SECOND_CORE_BOOT_ADDRESS_MCUX)
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/**
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*
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* @brief Slave Init
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*
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* This routine boots the secondary core
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*
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* @retval 0 on success.
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*
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*/
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/* This function is also called at deep sleep resume. */
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int _slave_init(void)
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{
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int32_t temp;
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/* Enable SRAM2, used by other core */
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SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
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/* Copy second core image to SRAM */
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LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;));
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/* Setup the reset handler pointer (PC) and stack pointer value.
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* This is used once the second core runs its startup code.
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* The second core first boots from flash (address 0x00000000)
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* and then detects its identity (Cortex-M0, slave) and checks
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* registers CPBOOT and CPSTACK and use them to continue the
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* boot process.
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* Make sure the startup code for the current core (Cortex-M4) is
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* appropriate and shareable with the Cortex-M0 core!
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*/
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SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(
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*(uint32_t *)((uint8_t *)CORE_M0_BOOT_ADDRESS + 0x4));
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SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(
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*(uint32_t *)CORE_M0_BOOT_ADDRESS);
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/* Reset the secondary core and start its clocks */
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temp = SYSCON->CPUCTRL;
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temp |= 0xc0c48000;
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SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK
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| SYSCON_CPUCTRL_CM0RSTEN_MASK);
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SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK)
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& (~SYSCON_CPUCTRL_CM0RSTEN_MASK);
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return 0;
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}
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SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /*CONFIG_SECOND_CORE_MCUX && CONFIG_SOC_LPC54114_M4 */
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