102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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/*
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* Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
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* inputs.
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*/
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static int soc_ecia_init(void)
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{
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GIRQ_Type *pg;
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uint32_t n;
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mchp_pcr_periph_slp_ctrl(PCR_ECIA, MCHP_PCR_SLEEP_DIS);
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ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN;
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/* gate off all aggregated outputs */
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ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul;
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/* gate on GIRQ's that are aggregated only */
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ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP;
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/* Clear all GIRQn source enables and source status */
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pg = &ECIA_REGS->GIRQ08;
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for (n = MCHP_FIRST_GIRQ; n <= MCHP_LAST_GIRQ; n++) {
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pg->EN_CLR = 0xFFFFFFFFul;
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pg->SRC = 0xFFFFFFFFul;
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pg++;
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}
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/* Clear all external NVIC enables and pending status */
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for (n = 0u; n < MCHP_NUM_NVIC_REGS; n++) {
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NVIC->ICER[n] = 0xFFFFFFFFul;
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NVIC->ICPR[n] = 0xFFFFFFFFul;
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}
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return 0;
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}
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static void configure_debug_interface(void)
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{
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/* No debug support */
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ECS_REGS->DEBUG_CTRL = 0;
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ECS_REGS->ETM_CTRL = 0;
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#ifdef CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING
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/* Release JTAG TDI and JTAG TDO pins so they can be
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* controlled by their respective PCR register (UART2).
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* For more details see table 44-1
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*/
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ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN |
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MCHP_ECS_DCTRL_MODE_SWD);
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#elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_TRACING)
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#if defined(CONFIG_SOC_MEC1501_DEBUG_AND_ETM_TRACING)
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#pragma error "TRACE DATA are not exposed in HW connector"
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#elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_SWV_TRACING)
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ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN |
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MCHP_ECS_DCTRL_MODE_SWD_SWV);
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#endif /* CONFIG_SOC_MEC1501_DEBUG_AND_TRACING */
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#endif /* CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING */
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}
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static int soc_init(void)
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{
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uint32_t isave;
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isave = __get_PRIMASK();
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__disable_irq();
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soc_ecia_init();
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/* Configure GPIO bank before usage
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* VTR1 is not configurable
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* VTR2 doesn't need configuration if setting VTR2_STRAP
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*/
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#ifdef CONFIG_SOC_MEC1501_VTR3_1_8V
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ECS_REGS->GPIO_BANK_PWR |= MCHP_ECS_VTR3_LVL_18;
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#endif
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configure_debug_interface();
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if (!isave) {
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__enable_irq();
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}
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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