145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
/*
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* Copyright (c) 2019 Microchip Technology Inc.
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/pm/pm.h>
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#include <soc.h>
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#include "device_power.h"
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/*
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* Deep Sleep
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* Pros:
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* Lower power dissipation, 48MHz PLL is off
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* Cons:
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* Longer wake latency. CPU start running on ring oscillator
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* between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
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* frequency of 48MHz.
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*
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* Implementation Notes:
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* We touch the Cortex-M's primary mask and base priority registers
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* because we do not want to enter an ISR immediately upon wake.
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* We must restore any hardware state that was modified upon sleep
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* entry before allowing interrupts to be serviced. Zephyr arch level
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* does not provide API's to manipulate both primary mask and base priority.
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*
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* DEBUG NOTES:
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* If a JTAG/SWD debug probe is connected driving TRST# high and
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* possibly polling the DUT then MEC1501 will not shut off its 48MHz
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* PLL. Firmware should not disable JTAG/SWD in the EC subsystem
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* while a probe is using the interface. This can leave the JTAG/SWD
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* TAP controller in a state of requesting clocks preventing the PLL
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* from being shut off.
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*/
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static void z_power_soc_deep_sleep(void)
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{
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/* Mask all exceptions and interrupts except NMI and HardFault */
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__set_PRIMASK(1);
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soc_deep_sleep_periph_save();
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soc_deep_sleep_enable();
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soc_deep_sleep_wait_clk_idle();
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soc_deep_sleep_non_wake_en();
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/*
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* Unmask all interrupts in BASEPRI. PRIMASK is used above to
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* prevent entering an ISR after unmasking in BASEPRI.
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*/
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__set_BASEPRI(0);
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barrier_dsync_fence_full();
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__WFI(); /* triggers sleep hardware */
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__NOP();
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__NOP();
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soc_deep_sleep_disable();
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soc_deep_sleep_non_wake_dis();
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/* Wait for PLL to lock */
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while ((PCR_REGS->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) {
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}
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soc_deep_sleep_periph_restore();
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/*
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* pm_state_exit_post_ops() is not being called
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* after exiting deep sleep, so need to unmask exceptions
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* and interrupts here.
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*/
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__set_PRIMASK(0);
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}
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/*
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* Light Sleep
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* Pros:
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* Fast wake response:
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* Cons:
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* Higher power dissipation, 48MHz PLL remains on.
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*/
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static void z_power_soc_sleep(void)
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{
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__set_PRIMASK(1);
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soc_lite_sleep_enable();
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__set_BASEPRI(0); /* Make sure wake interrupts are not masked! */
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barrier_dsync_fence_full();
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__WFI(); /* triggers sleep hardware */
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__NOP();
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__NOP();
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}
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/*
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* Called from pm_system_suspend(int32_t ticks) in subsys/power.c
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* For deep sleep pm_system_suspend has executed all the driver
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* power management call backs.
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*/
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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z_power_soc_sleep();
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break;
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case PM_STATE_SUSPEND_TO_RAM:
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z_power_soc_deep_sleep();
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break;
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default:
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break;
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}
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}
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/*
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* Zephyr PM code expects us to enabled interrupts at post op exit. Zephyr used
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* arch_irq_lock() which sets BASEPRI to a non-zero value masking all interrupts
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* preventing wake. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
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* allowing wake from any enabled interrupt and prevents the CPU from entering
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* an ISR on wake except for faults. We re-enable interrupts by setting PRIMASK
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* to 0.
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*/
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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case PM_STATE_SUSPEND_TO_RAM:
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__set_PRIMASK(0);
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barrier_isync_fence_full();
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break;
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default:
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irq_unlock(0);
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break;
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}
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}
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