134 lines
4.7 KiB
C
134 lines
4.7 KiB
C
/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_fmc_sdram
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#include <device.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(memc_stm32_sdram, CONFIG_MEMC_LOG_LEVEL);
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/** SDRAM controller register offset. */
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#define SDRAM_OFFSET 0x140U
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/** FMC SDRAM controller bank configuration fields. */
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struct memc_stm32_sdram_bank_config {
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FMC_SDRAM_InitTypeDef init;
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FMC_SDRAM_TimingTypeDef timing;
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};
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/** FMC SDRAM controller configuration fields. */
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struct memc_stm32_sdram_config {
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FMC_SDRAM_TypeDef *sdram;
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uint32_t power_up_delay;
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uint8_t num_auto_refresh;
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uint16_t mode_register;
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uint16_t refresh_rate;
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const struct memc_stm32_sdram_bank_config *banks;
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size_t banks_len;
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};
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static int memc_stm32_sdram_init(const struct device *dev)
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{
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const struct memc_stm32_sdram_config *config = dev->config;
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SDRAM_HandleTypeDef sdram = { 0 };
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FMC_SDRAM_CommandTypeDef sdram_cmd = { 0 };
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sdram.Instance = config->sdram;
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for (size_t i = 0U; i < config->banks_len; i++) {
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sdram.State = HAL_SDRAM_STATE_RESET;
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memcpy(&sdram.Init, &config->banks[i].init, sizeof(sdram.Init));
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(void)HAL_SDRAM_Init(
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&sdram,
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(FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing);
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}
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/* SDRAM initialization sequence */
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if (config->banks_len == 2U) {
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sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
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} else if (config->banks[0].init.SDBank == FMC_SDRAM_BANK1) {
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sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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} else {
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sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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}
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sdram_cmd.AutoRefreshNumber = config->num_auto_refresh;
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sdram_cmd.ModeRegisterDefinition = config->mode_register;
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/* enable clock */
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sdram_cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
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k_usleep(config->power_up_delay);
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/* pre-charge all */
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sdram_cmd.CommandMode = FMC_SDRAM_CMD_PALL;
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(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
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/* auto-refresh */
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sdram_cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
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/* load mode */
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sdram_cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
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/* program refresh count */
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(void)HAL_SDRAM_ProgramRefreshRate(&sdram, config->refresh_rate);
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return 0;
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}
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/** SDRAM bank/s configuration initialization macro. */
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#define BANK_CONFIG(node_id) \
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{ .init = { \
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.SDBank = DT_REG_ADDR(node_id), \
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.ColumnBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 0), \
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.RowBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 1), \
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.MemoryDataWidth = DT_PROP_BY_IDX(node_id, st_sdram_control, 2), \
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.InternalBankNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 3),\
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.CASLatency = DT_PROP_BY_IDX(node_id, st_sdram_control, 4), \
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.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE, \
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.SDClockPeriod = DT_PROP_BY_IDX(node_id, st_sdram_control, 5), \
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.ReadBurst = DT_PROP_BY_IDX(node_id, st_sdram_control, 6), \
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.ReadPipeDelay = DT_PROP_BY_IDX(node_id, st_sdram_control, 7), \
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}, \
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.timing = { \
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.LoadToActiveDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 0), \
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.ExitSelfRefreshDelay = \
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DT_PROP_BY_IDX(node_id, st_sdram_timing, 1), \
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.SelfRefreshTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 2), \
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.RowCycleDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 3), \
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.WriteRecoveryTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 4), \
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.RPDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 5), \
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.RCDDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 6), \
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} \
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},
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/** SDRAM bank/s configuration. */
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static const struct memc_stm32_sdram_bank_config bank_config[] = {
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DT_INST_FOREACH_CHILD(0, BANK_CONFIG)
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};
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/** SDRAM configuration. */
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static const struct memc_stm32_sdram_config config = {
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.sdram = (FMC_SDRAM_TypeDef *)(DT_REG_ADDR(DT_PARENT(DT_DRV_INST(0))) +
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SDRAM_OFFSET),
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.power_up_delay = DT_INST_PROP(0, power_up_delay),
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.num_auto_refresh = DT_INST_PROP(0, num_auto_refresh),
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.mode_register = DT_INST_PROP(0, mode_register),
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.refresh_rate = DT_INST_PROP(0, refresh_rate),
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.banks = bank_config,
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.banks_len = ARRAY_SIZE(bank_config),
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};
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DEVICE_DT_INST_DEFINE(0, memc_stm32_sdram_init, NULL,
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NULL, &config, POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY, NULL);
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