135 lines
4.1 KiB
C
135 lines
4.1 KiB
C
/*
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* Copyright (c) 2018 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Serial Wire Output (SWO) backend implementation.
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*
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* SWO/SWV has been developed by ARM. The following code works only on ARM
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* architecture.
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*
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* An SWO viewer program will typically set-up the SWO port including its
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* frequency when connected to the debug probe. Such configuration can persist
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* only until the MCU reset. The SWO backend initialization function will
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* re-configure the SWO port upon boot and set the frequency as specified by
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* the LOG_BACKEND_SWO_FREQ_HZ Kconfig option. To ensure flawless operation
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* this frequency should much the one set by the SWO viewer program.
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*
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* The initialization code assumes that SWO core frequency is equal to HCLK
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* as defined by DT_CPU_CLOCK_FREQUENCY. This may require additional,
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* vendor specific configuration.
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*/
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#include <logging/log_backend.h>
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#include <logging/log_core.h>
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#include <logging/log_msg.h>
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#include <logging/log_output.h>
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#include "log_backend_std.h"
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#include <soc.h>
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/** The stimulus port from which SWO data is received and displayed */
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#define ITM_PORT_LOGGER 0
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/* Set TPIU prescaler for the current debug trace clock frequency. */
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#if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0
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#define SWO_FREQ_DIV 1
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#else
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#define SWO_FREQ (DT_CPU_CLOCK_FREQUENCY + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2))
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#define SWO_FREQ_DIV (SWO_FREQ / CONFIG_LOG_BACKEND_SWO_FREQ_HZ)
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#if SWO_FREQ_DIV > 0xFFFF
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#error CONFIG_LOG_BACKEND_SWO_FREQ_HZ is too low. SWO clock divider is 16-bit. \
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Minimum supported SWO clock frequency is \
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[CPU Clock Frequency]/2^16.
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#endif
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#endif
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static u8_t buf[1];
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static int char_out(u8_t *data, size_t length, void *ctx)
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{
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ARG_UNUSED(ctx);
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for (size_t i = 0; i < length; i++) {
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ITM_SendChar(data[i]);
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}
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return length;
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}
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LOG_OUTPUT_DEFINE(log_output, char_out, buf, sizeof(buf));
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static void log_backend_swo_put(const struct log_backend *const backend,
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struct log_msg *msg)
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{
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log_backend_std_put(&log_output, 0, msg);
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}
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static void log_backend_swo_init(void)
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{
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/* Enable DWT and ITM units */
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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/* Enable access to ITM registers */
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ITM->LAR = 0xC5ACCE55;
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/* Disable stimulus ports ITM_STIM0-ITM_STIM31 */
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ITM->TER = 0x0;
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/* Disable ITM */
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ITM->TCR = 0x0;
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/* Select NRZ (UART) encoding protocol */
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TPI->SPPR = 2;
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/* Set SWO baud rate prescaler value: SWO_clk = ref_clock/(ACPR + 1) */
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TPI->ACPR = SWO_FREQ_DIV - 1;
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/* Enable unprivileged access to ITM stimulus ports */
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ITM->TPR = 0x0;
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/* Configure Debug Watchpoint and Trace */
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DWT->CTRL = 0x400003FE;
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/* Configure Formatter and Flush Control Register */
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TPI->FFCR = 0x00000100;
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/* Enable ITM, set TraceBusID=1, no local timestamp generation */
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ITM->TCR = 0x0001000D;
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/* Enable stimulus port used by the logger */
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ITM->TER = 1 << ITM_PORT_LOGGER;
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}
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static void log_backend_swo_panic(struct log_backend const *const backend)
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{
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}
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static void dropped(const struct log_backend *const backend, u32_t cnt)
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{
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ARG_UNUSED(backend);
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log_backend_std_dropped(&log_output, cnt);
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}
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static void log_backend_swo_sync_string(const struct log_backend *const backend,
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struct log_msg_ids src_level, u32_t timestamp,
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const char *fmt, va_list ap)
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{
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log_backend_std_sync_string(&log_output, 0, src_level,
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timestamp, fmt, ap);
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}
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static void log_backend_swo_sync_hexdump(
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const struct log_backend *const backend,
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struct log_msg_ids src_level, u32_t timestamp,
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const char *metadata, const u8_t *data, u32_t length)
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{
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log_backend_std_sync_hexdump(&log_output, 0, src_level,
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timestamp, metadata, data, length);
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}
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const struct log_backend_api log_backend_swo_api = {
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.put = IS_ENABLED(CONFIG_LOG_IMMEDIATE) ? NULL : log_backend_swo_put,
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.put_sync_string = IS_ENABLED(CONFIG_LOG_IMMEDIATE) ?
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log_backend_swo_sync_string : NULL,
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.put_sync_hexdump = IS_ENABLED(CONFIG_LOG_IMMEDIATE) ?
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log_backend_swo_sync_hexdump : NULL,
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.panic = log_backend_swo_panic,
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.init = log_backend_swo_init,
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.dropped = IS_ENABLED(CONFIG_LOG_IMMEDIATE) ? NULL : dropped,
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};
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LOG_BACKEND_DEFINE(log_backend_swo, log_backend_swo_api, true);
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