zephyr/soc/xtensa
Iuliana Prodan f9810ccbe1 arch: xtensa: modify asm for interrupt sections
For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.

I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2021-08-28 23:27:02 -04:00
..
esp32 soc: esp32: Fix symbol placement in linker script 2021-08-20 18:25:22 -04:00
esp32s2 esp32s2: drivers: gpio: add gpio support 2021-08-27 17:34:41 -04:00
intel_adsp linker: xtensa: move IDT_LIST region 2021-08-25 18:08:36 -04:00
intel_s1000 linker: xtensa: move IDT_LIST region 2021-08-25 18:08:36 -04:00
nxp_adsp arch: xtensa: modify asm for interrupt sections 2021-08-28 23:27:02 -04:00
sample_controller linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
CMakeLists.txt