Carles Cufi 1126bbdca0 dts: psoc6: Use valid IRQ prio levels for CM4 ... The psoc6 SoC has 2 cores, each with different allowed priority ranges: CM0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel) CM4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel) Since some of the peripherals are only available to the CM4, those should be set to a priority that is actually valid for it. In this case the lowest possible one is 6, so transition from 7 to 6. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>		2021-08-11 10:06:13 -05:00
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pinctrl_cypress_psoc6.h	dts: arm: cypress: Introduce PSoC-6 pinctrl	2021-03-16 13:36:15 -05:00
psoc6-pinctrl.dtsi	dts: spi: Add cypress PSoC-6 controller	2021-05-05 16:01:28 +02:00
psoc6.dtsi	dts: psoc6: Use valid IRQ prio levels for CM4	2021-08-11 10:06:13 -05:00
psoc6_cm0.dtsi	soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support	2021-01-20 17:54:09 -06:00
psoc6_cm4.dtsi	…