383 lines
11 KiB
C
383 lines
11 KiB
C
/* swap_macros.h - helper macros for context switch */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
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#define ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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#ifdef _ASMLANGUAGE
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/* entering this macro, current is in r2 */
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.macro _save_callee_saved_regs
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sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
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/* save regs on stack */
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st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
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st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
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st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
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st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
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st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
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st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
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st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
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st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
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st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
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st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
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st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
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st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
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st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
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st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
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st fp, [sp, ___callee_saved_stack_t_fp_OFFSET]
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_ARC_HAS_SECURE
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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lr r13, [_ARC_V2_SEC_U_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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lr r13, [_ARC_V2_SEC_K_SP]
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st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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#else
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lr r13, [_ARC_V2_USER_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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lr r13, [_ARC_V2_KERNEL_SP]
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st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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#else
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lr r13, [_ARC_V2_USER_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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#endif
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#endif
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st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
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st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
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#endif
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#ifdef CONFIG_FP_SHARING
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ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
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/* K_FP_REGS is bit 1 */
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bbit0 r13, 1, 1f
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lr r13, [_ARC_V2_FPU_STATUS]
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st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
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lr r13, [_ARC_V2_FPU_CTRL]
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st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
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#ifdef CONFIG_FP_FPU_DA
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lr r13, [_ARC_V2_FPU_DPFP1L]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP1H]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP2L]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP2H]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
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#endif
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1 :
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#endif
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/* save stack pointer in struct k_thread */
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st sp, [r2, _thread_offset_to_sp]
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.endm
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/* entering this macro, current is in r2 */
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.macro _load_callee_saved_regs
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/* restore stack pointer from struct k_thread */
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ld sp, [r2, _thread_offset_to_sp]
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
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ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
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#endif
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#ifdef CONFIG_FP_SHARING
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ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
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/* K_FP_REGS is bit 1 */
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bbit0 r13, 1, 2f
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ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
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sr r13, [_ARC_V2_FPU_STATUS]
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ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
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sr r13, [_ARC_V2_FPU_CTRL]
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#ifdef CONFIG_FP_FPU_DA
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP1L]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP1H]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP2L]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP2H]
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#endif
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2 :
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#endif
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_ARC_HAS_SECURE
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_SEC_U_SP]
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ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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sr r13, [_ARC_V2_SEC_K_SP]
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#else
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_USER_SP]
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ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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sr r13, [_ARC_V2_KERNEL_SP]
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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#else
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_USER_SP]
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#endif
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#endif
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ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
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ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
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ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
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ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
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ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
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ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
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ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
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ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
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ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
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ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
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ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
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ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
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ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
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ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
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ld fp, [sp, ___callee_saved_stack_t_fp_OFFSET]
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ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
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add_s sp, sp, ___callee_saved_stack_t_SIZEOF
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.endm
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.macro _discard_callee_saved_regs
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add_s sp, sp, ___callee_saved_stack_t_SIZEOF
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.endm
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/*
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* Must be called with interrupts locked or in P0.
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* Upon exit, sp will be pointing to the stack frame.
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*/
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.macro _create_irq_stack_frame
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sub_s sp, sp, ___isf_t_SIZEOF
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st blink, [sp, ___isf_t_blink_OFFSET]
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/* store these right away so we can use them if needed */
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st_s r13, [sp, ___isf_t_r13_OFFSET]
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st_s r12, [sp, ___isf_t_r12_OFFSET]
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st r11, [sp, ___isf_t_r11_OFFSET]
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st r10, [sp, ___isf_t_r10_OFFSET]
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st r9, [sp, ___isf_t_r9_OFFSET]
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st r8, [sp, ___isf_t_r8_OFFSET]
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st r7, [sp, ___isf_t_r7_OFFSET]
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st r6, [sp, ___isf_t_r6_OFFSET]
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st r5, [sp, ___isf_t_r5_OFFSET]
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st r4, [sp, ___isf_t_r4_OFFSET]
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st_s r3, [sp, ___isf_t_r3_OFFSET]
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st_s r2, [sp, ___isf_t_r2_OFFSET]
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st_s r1, [sp, ___isf_t_r1_OFFSET]
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st_s r0, [sp, ___isf_t_r0_OFFSET]
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mov r0, lp_count
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st_s r0, [sp, ___isf_t_lp_count_OFFSET]
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lr r1, [_ARC_V2_LP_START]
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lr r0, [_ARC_V2_LP_END]
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st_s r1, [sp, ___isf_t_lp_start_OFFSET]
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st_s r0, [sp, ___isf_t_lp_end_OFFSET]
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#ifdef CONFIG_CODE_DENSITY
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lr r1, [_ARC_V2_JLI_BASE]
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lr r0, [_ARC_V2_LDI_BASE]
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lr r2, [_ARC_V2_EI_BASE]
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st_s r1, [sp, ___isf_t_jli_base_OFFSET]
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st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
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st_s r2, [sp, ___isf_t_ei_base_OFFSET]
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#endif
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.endm
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/*
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* Must be called with interrupts locked or in P0.
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* sp must be pointing the to stack frame.
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*/
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.macro _pop_irq_stack_frame
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ld blink, [sp, ___isf_t_blink_OFFSET]
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#ifdef CONFIG_CODE_DENSITY
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ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
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ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
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ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
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sr r1, [_ARC_V2_JLI_BASE]
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sr r0, [_ARC_V2_LDI_BASE]
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sr r2, [_ARC_V2_EI_BASE]
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#endif
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ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
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mov lp_count, r0
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ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
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ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
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sr r1, [_ARC_V2_LP_START]
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sr r0, [_ARC_V2_LP_END]
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ld_s r13, [sp, ___isf_t_r13_OFFSET]
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ld_s r12, [sp, ___isf_t_r12_OFFSET]
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ld r11, [sp, ___isf_t_r11_OFFSET]
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ld r10, [sp, ___isf_t_r10_OFFSET]
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ld r9, [sp, ___isf_t_r9_OFFSET]
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ld r8, [sp, ___isf_t_r8_OFFSET]
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ld r7, [sp, ___isf_t_r7_OFFSET]
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ld r6, [sp, ___isf_t_r6_OFFSET]
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ld r5, [sp, ___isf_t_r5_OFFSET]
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ld r4, [sp, ___isf_t_r4_OFFSET]
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ld_s r3, [sp, ___isf_t_r3_OFFSET]
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ld_s r2, [sp, ___isf_t_r2_OFFSET]
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ld_s r1, [sp, ___isf_t_r1_OFFSET]
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ld_s r0, [sp, ___isf_t_r0_OFFSET]
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/*
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* All gprs have been reloaded, the only one that is still usable is
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* ilink.
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*
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* The pc and status32 values will still be on the stack. We cannot
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* pop them yet because the callers of _pop_irq_stack_frame must reload
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* status32 differently depending on the execution context they are
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* running in (z_arch_switch(), firq or exception).
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*/
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add_s sp, sp, ___isf_t_SIZEOF
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.endm
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/*
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* To use this macor, r2 should have the value of thread struct pointer to
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* _kernel.current. r3 is a scratch reg.
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*/
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.macro _load_stack_check_regs
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#if defined(CONFIG_ARC_SECURE_FIRMWARE)
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ld r3, [r2, _thread_offset_to_k_stack_base]
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sr r3, [_ARC_V2_S_KSTACK_BASE]
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ld r3, [r2, _thread_offset_to_k_stack_top]
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sr r3, [_ARC_V2_S_KSTACK_TOP]
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#ifdef CONFIG_USERSPACE
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ld r3, [r2, _thread_offset_to_u_stack_base]
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sr r3, [_ARC_V2_S_USTACK_BASE]
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ld r3, [r2, _thread_offset_to_u_stack_top]
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sr r3, [_ARC_V2_S_USTACK_TOP]
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#endif
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#else /* CONFIG_ARC_HAS_SECURE */
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ld r3, [r2, _thread_offset_to_k_stack_base]
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sr r3, [_ARC_V2_KSTACK_BASE]
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ld r3, [r2, _thread_offset_to_k_stack_top]
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sr r3, [_ARC_V2_KSTACK_TOP]
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#ifdef CONFIG_USERSPACE
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ld r3, [r2, _thread_offset_to_u_stack_base]
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sr r3, [_ARC_V2_USTACK_BASE]
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ld r3, [r2, _thread_offset_to_u_stack_top]
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sr r3, [_ARC_V2_USTACK_TOP]
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#endif
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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.endm
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/* check and increase the interrupt nest counter
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* after increase, check whether nest counter == 1
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* the result will be EQ bit of status32
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*/
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.macro _check_and_inc_int_nest_counter reg1 reg2
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#ifdef CONFIG_SMP
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_get_cpu_id \reg1
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ld.as \reg1, [@_curr_cpu, \reg1]
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ld \reg2, [\reg1, ___cpu_t_nested_OFFSET]
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#else
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mov \reg1, _kernel
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ld \reg2, [\reg1, ___kernel_t_nested_OFFSET]
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#endif
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add \reg2, \reg2, 1
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#ifdef CONFIG_SMP
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st \reg2, [\reg1, ___cpu_t_nested_OFFSET]
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#else
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st \reg2, [\reg1, ___kernel_t_nested_OFFSET]
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#endif
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cmp \reg2, 1
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.endm
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/* decrease interrupt nest counter */
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.macro _dec_int_nest_counter reg1 reg2
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#ifdef CONFIG_SMP
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_get_cpu_id \reg1
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ld.as \reg1, [@_curr_cpu, \reg1]
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ld \reg2, [\reg1, ___cpu_t_nested_OFFSET]
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#else
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mov \reg1, _kernel
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ld \reg2, [\reg1, ___kernel_t_nested_OFFSET]
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#endif
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sub \reg2, \reg2, 1
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#ifdef CONFIG_SMP
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st \reg2, [\reg1, ___cpu_t_nested_OFFSET]
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#else
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st \reg2, [\reg1, ___kernel_t_nested_OFFSET]
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#endif
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.endm
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/* If multi bits in IRQ_ACT are set, i.e. last bit != fist bit, it's
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* in nest interrupt. The result will be EQ bit of status32
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*/
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.macro _check_nest_int_by_irq_act reg1, reg2
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lr \reg1, [_ARC_V2_AUX_IRQ_ACT]
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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and \reg1, \reg1, ((1 << ARC_N_IRQ_START_LEVEL) - 1)
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#else
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and \reg1, \reg1, 0xffff
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#endif
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ffs \reg2, \reg1
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fls \reg1, \reg1
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cmp \reg1, \reg2
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.endm
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.macro _get_cpu_id reg
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lr \reg, [_ARC_V2_IDENTITY]
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xbfu \reg, \reg, 0xe8
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.endm
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.macro _get_curr_cpu_irq_stack irq_sp
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#ifdef CONFIG_SMP
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_get_cpu_id \irq_sp
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ld.as \irq_sp, [@_curr_cpu, \irq_sp]
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ld \irq_sp, [\irq_sp, ___cpu_t_irq_stack_OFFSET]
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#else
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mov \irq_sp, _kernel
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ld \irq_sp, [\irq_sp, _kernel_offset_to_irq_stack]
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#endif
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.endm
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/* macro to push aux reg through reg */
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.macro PUSHAX reg aux
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lr \reg, [\aux]
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st.a \reg, [sp, -4]
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.endm
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/* macro to pop aux reg through reg */
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.macro POPAX reg aux
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ld.ab \reg, [sp, 4]
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sr \reg, [\aux]
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.endm
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_ */
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