228 lines
6.7 KiB
C
228 lines
6.7 KiB
C
/* spi_dw.h - Designware SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SPI_SPI_DW_H_
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#define ZEPHYR_DRIVERS_SPI_SPI_DW_H_
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#include <string.h>
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#include <zephyr/drivers/spi.h>
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#include "spi_context.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*spi_dw_config_t)(void);
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/* Private structures */
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struct spi_dw_config {
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uint32_t regs;
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uint32_t clock_frequency;
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spi_dw_config_t config_func;
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uint8_t op_modes;
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};
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struct spi_dw_data {
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struct spi_context ctx;
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uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
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uint8_t fifo_diff; /* cannot be bigger than FIFO depth */
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uint16_t _unused;
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};
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/* Helper macros */
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#define SPI_DW_CLK_DIVIDER(clock_freq, ssi_clk_hz) \
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((clock_freq / ssi_clk_hz) & 0xFFFF)
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#ifdef CONFIG_SPI_DW_ARC_AUX_REGS
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#define Z_REG_READ(__sz) sys_in##__sz
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#define Z_REG_WRITE(__sz) sys_out##__sz
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#define Z_REG_SET_BIT sys_io_set_bit
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#define Z_REG_CLEAR_BIT sys_io_clear_bit
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#define Z_REG_TEST_BIT sys_io_test_bit
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#else
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#define Z_REG_READ(__sz) sys_read##__sz
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#define Z_REG_WRITE(__sz) sys_write##__sz
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#define Z_REG_SET_BIT sys_set_bit
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#define Z_REG_CLEAR_BIT sys_clear_bit
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#define Z_REG_TEST_BIT sys_test_bit
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#endif /* CONFIG_SPI_DW_ARC_AUX_REGS */
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#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
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static inline uint32_t read_##__reg(uint32_t addr) \
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{ \
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return Z_REG_READ(__sz)(addr + __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
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static inline void write_##__reg(uint32_t data, uint32_t addr) \
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{ \
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Z_REG_WRITE(__sz)(data, addr + __off); \
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}
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#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void set_bit_##__reg_bit(uint32_t addr) \
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{ \
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Z_REG_SET_BIT(addr + __reg_off, __bit); \
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}
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#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void clear_bit_##__reg_bit(uint32_t addr) \
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{ \
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Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \
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}
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#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline int test_bit_##__reg_bit(uint32_t addr) \
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{ \
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return Z_REG_TEST_BIT(addr + __reg_off, __bit); \
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}
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/* Common registers settings, bits etc... */
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/* CTRLR0 settings */
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#define DW_SPI_CTRLR0_SCPH_BIT (6)
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#define DW_SPI_CTRLR0_SCPOL_BIT (7)
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#define DW_SPI_CTRLR0_SRL_BIT (11)
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#define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT)
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#define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
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#define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
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#define DW_SPI_CTRLR0_SLV_OE_BIT (10)
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#define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
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#ifdef CONFIG_SOC_INTEL_S1000
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#define DW_SPI_CTRLR0_TMOD_SHIFT (10)
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#else
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#define DW_SPI_CTRLR0_TMOD_SHIFT (8)
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#endif
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#define DW_SPI_CTRLR0_TMOD_TX_RX (0)
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#define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_RX (2 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_EEPROM (3 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_RESET (3 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1)
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#define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16)
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#if defined(CONFIG_ARC) || defined(CONFIG_SOC_INTEL_S1000)
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#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_16
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#else
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#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_32
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#endif
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/* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
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* These are the bits were when you divide by 8, you keep the result as it is.
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* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
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* since on such division it takes only the result above 0
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*/
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#define SPI_WS_TO_DFS(__bpw) (((__bpw) & ~0x38) ? \
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(((__bpw) / 8) + 1) : \
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((__bpw) / 8))
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/* SSIENR bits */
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#define DW_SPI_SSIENR_SSIEN_BIT (0)
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/* SR bits and values */
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#define DW_SPI_SR_BUSY_BIT (0)
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#define DW_SPI_SR_TFNF_BIT (1)
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#define DW_SPI_SR_RFNE_BIT (3)
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/* IMR bits (ISR valid as well) */
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#define DW_SPI_IMR_TXEIM_BIT (0)
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#define DW_SPI_IMR_TXOIM_BIT (1)
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#define DW_SPI_IMR_RXUIM_BIT (2)
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#define DW_SPI_IMR_RXOIM_BIT (3)
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#define DW_SPI_IMR_RXFIM_BIT (4)
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#define DW_SPI_IMR_MSTIM_BIT (5)
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/* IMR values */
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#define DW_SPI_IMR_TXEIM BIT(DW_SPI_IMR_TXEIM_BIT)
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#define DW_SPI_IMR_TXOIM BIT(DW_SPI_IMR_TXOIM_BIT)
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#define DW_SPI_IMR_RXUIM BIT(DW_SPI_IMR_RXUIM_BIT)
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#define DW_SPI_IMR_RXOIM BIT(DW_SPI_IMR_RXOIM_BIT)
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#define DW_SPI_IMR_RXFIM BIT(DW_SPI_IMR_RXFIM_BIT)
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#define DW_SPI_IMR_MSTIM BIT(DW_SPI_IMR_MSTIM_BIT)
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/* ISR values (same as IMR) */
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#define DW_SPI_ISR_TXEIS DW_SPI_IMR_TXEIM
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#define DW_SPI_ISR_TXOIS DW_SPI_IMR_TXOIM
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#define DW_SPI_ISR_RXUIS DW_SPI_IMR_RXUIM
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#define DW_SPI_ISR_RXOIS DW_SPI_IMR_RXOIM
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#define DW_SPI_ISR_RXFIS DW_SPI_IMR_RXFIM
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#define DW_SPI_ISR_MSTIS DW_SPI_IMR_MSTIM
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/* Error interrupt */
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#define DW_SPI_ISR_ERRORS_MASK (DW_SPI_ISR_TXOIS | \
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DW_SPI_ISR_RXUIS | \
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DW_SPI_ISR_RXOIS | \
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DW_SPI_ISR_MSTIS)
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/* ICR Bit */
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#define DW_SPI_SR_ICR_BIT (0)
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/* Threshold defaults */
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#define DW_SPI_FIFO_DEPTH CONFIG_SPI_DW_FIFO_DEPTH
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#define DW_SPI_TXFTLR_DFLT ((DW_SPI_FIFO_DEPTH * 1) / 2) /* 50% */
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#define DW_SPI_RXFTLR_DFLT ((DW_SPI_FIFO_DEPTH * 5) / 8)
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/* Interrupt mask (IMR) */
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#define DW_SPI_IMR_MASK (0x0)
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#define DW_SPI_IMR_UNMASK (DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM | \
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DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM)
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#define DW_SPI_IMR_MASK_TX (~(DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM))
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#define DW_SPI_IMR_MASK_RX (~(DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM))
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/*
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* Including the right register definition file
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* SoC SPECIFIC!
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*
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* The file included next uses the DEFINE_MM_REG macros above to
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* declare functions. In this situation we'll leave the containing
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* extern "C" active in C++ compilations.
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*/
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#include "spi_dw_regs.h"
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#define z_extra_clock_on(...)
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#define z_extra_clock_off(...)
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/* Based on those macros above, here are common helpers for some registers */
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DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32)
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DEFINE_MM_REG_READ(rxflr, DW_SPI_REG_RXFLR, 32)
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#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
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DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 32)
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DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 32)
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DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 32)
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DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 32)
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#else
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DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
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DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
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DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 8)
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DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)
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#endif
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DEFINE_SET_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_TEST_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_SPI_SPI_DW_H_ */
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