143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* Copyright (c) 2021 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT telink_b91_pwm
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#include "pwm.h"
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#include "clock.h"
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#include <drivers/pwm.h>
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#include <drivers/pinmux.h>
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#include <dt-bindings/pinctrl/b91-pinctrl.h>
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#define PWM_PCLK_SPEED DT_INST_PROP(0, clock_frequency)
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#define NUM_OF_CHANNELS DT_INST_PROP(0, channels)
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static const uint32_t pwm_pins[] = B91_PINMUX_DT_INST_GET_ARRAY(0, 0);
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/* API implementation: init */
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static int pwm_b91_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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uint8_t clk_32k_en = 0;
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uint32_t pwm_clk_div = 0;
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const struct device *pinmux;
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/* Calculate and check PWM clock divider */
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pwm_clk_div = sys_clk.pclk * 1000 * 1000 / PWM_PCLK_SPEED - 1;
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if (pwm_clk_div > 255) {
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return -EINVAL;
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}
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/* Set PWM Peripheral clock */
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pwm_set_clk((unsigned char) (pwm_clk_div & 0xFF));
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/* Set PWM 32k Channel clock if enabled */
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch0_enable) ? PWM_CLOCK_32K_CHN_PWM0 : 0;
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch1_enable) ? PWM_CLOCK_32K_CHN_PWM1 : 0;
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch2_enable) ? PWM_CLOCK_32K_CHN_PWM2 : 0;
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch3_enable) ? PWM_CLOCK_32K_CHN_PWM3 : 0;
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch4_enable) ? PWM_CLOCK_32K_CHN_PWM4 : 0;
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clk_32k_en |= DT_INST_PROP(0, clk32k_ch5_enable) ? PWM_CLOCK_32K_CHN_PWM5 : 0;
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pwm_32k_chn_en(clk_32k_en);
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/* Get PinMux driver */
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pinmux = DEVICE_DT_GET(DT_NODELABEL(pinmux));
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if (!device_is_ready(pinmux)) {
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return -ENODEV;
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}
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/* Config PWM pins */
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for (int i = 0; i < ARRAY_SIZE(pwm_pins); i++) {
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pinmux_pin_set(pinmux, B91_PINMUX_GET_PIN(pwm_pins[i]),
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B91_PINMUX_GET_FUNC(pwm_pins[i]));
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}
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return 0;
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}
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/* API implementation: pin_set */
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static int pwm_b91_pin_set(const struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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ARG_UNUSED(dev);
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/* check pwm channel */
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if (pwm >= NUM_OF_CHANNELS) {
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return -EINVAL;
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}
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/* check size of pulse and period (2 bytes) */
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if ((period_cycles > 0xFFFFu) ||
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(pulse_cycles > 0xFFFFu)) {
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return -EINVAL;
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}
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/* set polarity */
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if (flags & PWM_POLARITY_INVERTED) {
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pwm_invert_en(pwm);
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} else {
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pwm_invert_dis(pwm);
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}
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/* set pulse and period */
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pwm_set_tcmp(pwm, pulse_cycles);
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pwm_set_tmax(pwm, period_cycles);
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/* start pwm */
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pwm_start(pwm);
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return 0;
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}
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/* API implementation: get_cycles_per_sec */
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static int pwm_b91_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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ARG_UNUSED(dev);
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/* check pwm channel */
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if (pwm >= NUM_OF_CHANNELS) {
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return -EINVAL;
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}
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if (
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((pwm == 0u) && DT_INST_PROP(0, clk32k_ch0_enable)) ||
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((pwm == 1u) && DT_INST_PROP(0, clk32k_ch1_enable)) ||
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((pwm == 2u) && DT_INST_PROP(0, clk32k_ch2_enable)) ||
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((pwm == 3u) && DT_INST_PROP(0, clk32k_ch3_enable)) ||
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((pwm == 4u) && DT_INST_PROP(0, clk32k_ch4_enable)) ||
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((pwm == 5u) && DT_INST_PROP(0, clk32k_ch5_enable))
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) {
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*cycles = 32000u;
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} else {
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*cycles = sys_clk.pclk * 1000 * 1000 / (reg_pwm_clkdiv + 1);
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}
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return 0;
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}
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/* PWM driver APIs structure */
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static const struct pwm_driver_api pwm_b91_driver_api = {
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.pin_set = pwm_b91_pin_set,
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.get_cycles_per_sec = pwm_b91_get_cycles_per_sec,
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};
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
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"unsupported PWM instance");
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/* PWM driver registration */
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#define PWM_B91_INIT(n) \
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\
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DEVICE_DT_INST_DEFINE(n, pwm_b91_init, \
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NULL, NULL, NULL, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&pwm_b91_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_B91_INIT)
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