zephyr/soc/xtensa/intel_s1000
Andy Ross c174ade4a1 arch/xtensa: Rework irq_offload: automatic config, SMP-safe
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).

Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-02-21 22:10:03 -05:00
..
include soc/intel_s1000: Add new cAVS shim & IDC interfaces 2021-12-07 12:06:21 -05:00
soc soc: intel_s1000: Catch up with API skew 2020-10-21 06:38:53 -04:00
xcc soc: intel_s1000: remove log and ztest XCC fixes 2021-03-26 11:19:52 -05:00
CMakeLists.txt
Kconfig.defconfig arch/xtensa: Rework irq_offload: automatic config, SMP-safe 2022-02-21 22:10:03 -05:00
Kconfig.soc xtensa: intel_s1000: enable thread local storage 2020-10-24 10:52:00 -07:00
iomux.h
linker.ld soc: xtensa: cavs-link.ld: add *(.trace_ctx) sections 2021-12-22 17:47:21 -06:00
memory.h Revert "linker: xtensa: move IDT_LIST region" 2021-09-08 20:29:53 -05:00
soc.c arch/xtensa: General cleanup, remove dead code 2021-03-08 11:14:27 -05:00
soc.h arch/xtensa: Add non-HAL caching primitives 2021-03-08 11:14:27 -05:00
soc_mp.c arch/xtensa: Use ZSR assignments for the CPU pointer 2022-01-20 12:58:00 -05:00