Andy Ross c174ade4a1 arch/xtensa: Rework irq_offload: automatic config, SMP-safe ... The Xtensa implementation of arch_irq_offload() required that the user select the correct interrupt manually, and would race with itself if invoked from separate CPUs (it was saved here by the main irq_offload() function which has a semaphore to serialize access). Use the new gen_zsr.py script to automatically detect the highest available software interrupt, and keep a per-CPU set of callback/parameter pointers. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2022-02-21 22:10:03 -05:00
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include	soc: esp32s2: add initial soc support files for esp32s2	2021-07-28 21:09:27 -04:00
CMakeLists.txt	soc: esp32s2: refactor cache and bss initialization	2021-11-20 11:57:38 -05:00
Kconfig.defconfig	arch/xtensa: Rework irq_offload: automatic config, SMP-safe	2022-02-21 22:10:03 -05:00
Kconfig.soc	esp32 & esp32s2: lint: kconfig	2021-11-22 08:31:56 -05:00
linker.ld	soc: esp32s2: add SPI RAM support	2021-11-20 11:57:38 -05:00
soc.c	soc: esp32s2: fix: data cache setup	2021-12-03 16:45:16 -06:00
soc.h	soc: esp32s2: refactor cache and bss initialization	2021-11-20 11:57:38 -05:00
soc_cache.c	soc: esp32s2: refactor cache and bss initialization	2021-11-20 11:57:38 -05:00