zephyr/soc/xtensa/esp32
Andy Ross c174ade4a1 arch/xtensa: Rework irq_offload: automatic config, SMP-safe
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).

Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-02-21 22:10:03 -05:00
..
include
CMakeLists.txt soc: xtensa: esp32: fixes flash size reference 2022-02-07 13:22:25 -05:00
Kconfig.defconfig arch/xtensa: Rework irq_offload: automatic config, SMP-safe 2022-02-21 22:10:03 -05:00
Kconfig.soc soc: xtensa: esp32: fixes flash size reference 2022-02-07 13:22:25 -05:00
esp32-mp.c
gdbstub.c
linker.ld soc: esp32: Linker script updates to boot with MCUboot 2021-12-18 07:20:38 -05:00
loader.c soc: esp32: Update startup code to map IROM and DROM segments 2021-12-18 07:20:38 -05:00
soc.c soc: esp32: Update startup code to map IROM and DROM segments 2021-12-18 07:20:38 -05:00
soc.h soc: esp32: Update startup code to map IROM and DROM segments 2021-12-18 07:20:38 -05:00