128 lines
4.2 KiB
YAML
128 lines
4.2 KiB
YAML
# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The Ambiq Apollo3 pin controller is a node responsible for controlling
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pin function selection and pin properties, such as routing a UART0 TX
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to pin 60 and enabling the pullup resistor on that pin.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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pinmux = <UART0TX_P60>;
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};
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group2 {
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pinmux = <UART0RX_P47>;
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input-enable;
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};
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};
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};
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The 'uart0_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'pinmux'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'input-enable' property in group 2.
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compatible: "ambiq,apollo3-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- input-enable
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- drive-push-pull
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- drive-open-drain
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- bias-high-impedance
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- bias-pull-up
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- bias-pull-down
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properties:
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.
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drive-strength:
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type: string
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enum:
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- "0.1"
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- "0.5"
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- "0.75"
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- "1.0"
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default: "0.1"
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description: |
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The drive strength of a pin, relative to full-driver strength.
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The default value is 0.1, which is the reset value of resigers
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PADREGx.PADnSTRNG and ALTPADCFGx.PADn_DS1.
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ambiq,pull-up-ohms:
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type: int
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enum:
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- 1500
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- 6000
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- 12000
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- 24000
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default: 1500
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description: |
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The 1.5K-24K pullup values are valid for select I2C enabled pads.
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For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49.
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The default value is 1500 ohms, which is the reset value of
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register PADREGx.PADxRSEL.
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ambiq,iom-nce-module:
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type: int
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default: 0
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description: |
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IOM nCE module select, selects the SPI channel (CE) number (0-3).
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The default value is 0, which is the reset value of
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register CFGx.GPIOnOUTCFG. If the pin is not a CE, this
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descriptor will be ignored.
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ambiq,iom-mspi:
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type: int
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default: 0
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description: |
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Indicates the module which uses specific CE pin, 1 if CE is IOM, 0 if MSPI.
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User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
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information and config the pins accordingly, we give a default value
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0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
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ambiq hal. If the pin is not a CE, this descriptor will be ignored.
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ambiq,iom-num:
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type: int
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default: 0
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description: |
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Indicates the instance which uses specific CE pin.
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IOM number (0-5) or MSPI (0-2).
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User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
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information and config the pins accordingly, we give a default value
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0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
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ambiq hal. If the pin is not a CE, this descriptor will be ignored.
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