65 lines
2.2 KiB
YAML
65 lines
2.2 KiB
YAML
# Copyright (c) 2022 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 DMA controller for the stm32U5 soc family
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It is present on stm32U5 devices as a GP DMA
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This controller includes several channels with different requests.
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DMA clients connected to the STM32 DMA controller must use a three-cell
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specifier for each channel.
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For the client part, example for stm32u585 on GPDMA1 instance
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Tx using channel 0 with request 7
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Rx using channel 1 with request 6
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spi1 {
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dmas = <&gpdma1 0 7 0x10440>,
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<&gpdma1 1 6 0x10480>;
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dma-names = "tx", "rx";
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};
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It is a phandle to the DMA controller plus the following three integer cells
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1. channel: the stream or channel from 0 to (<dma-channels> - 1).
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2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
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the slot is a value between <0> .. (<dma-requests> - 1).
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3. channel-config: A 32bit mask specifying the DMA channel configuration
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which is device dependent:
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-bit 6-7 : Direction (see dma.h)
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0x0: MEM to MEM
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0x1: MEM to PERIPH
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0x2: PERIPH to MEM
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0x3: reserved for PERIPH to PERIPH
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-bit 9 : Peripheral Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 10 : Memory Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 11-12 : Peripheral data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: reserved
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-bit 13-14 : Memory data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: reserved
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-bit 15: Reserved
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-bit 16-17 : Priority level
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0x0: low
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0x1: medium
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0x2: high
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0x3: very high
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compatible: "st,stm32u5-dma"
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include: st,stm32-dma.yaml
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properties:
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"#dma-cells":
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const: 3
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dma-cells:
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- channel
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- slot
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- channel-config
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