91 lines
1.8 KiB
Plaintext
91 lines
1.8 KiB
Plaintext
/*
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* Copyright 2024 Myeonghyeon Park <myeonghyeon@tsnlab.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0>;
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};
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};
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interrupt-parent = <&gic>;
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <1>;
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sram0: memory@200000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x0 0x200000 0x80000>;
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};
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gic: interrupt-controller@107fff9000 {
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compatible = "arm,gic-v2", "arm,gic";
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reg = <0x10 0x7fff9000 0x1000>,
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<0x10 0x7fffa000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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gpio2@107d517c00 {
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compatible = "simple-bus";
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reg = <0x10 0x7d517c00 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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gio_aon: gpio@0 {
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compatible = "brcm,brcmstb-gpio";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <17>;
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status = "disabled";
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};
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};
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uart10: serial@107d001000 {
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compatible = "arm,pl011";
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reg = <0x10 0x7d001000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_121";
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clocks = <&clk_uart>;
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status = "disabled";
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};
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};
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clocks {
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clk_uart: clk_uart {
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compatible = "fixed-clock";
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clock-frequency = <44236800>;
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#clock-cells = <0>;
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};
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};
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};
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