208 lines
7.3 KiB
C
208 lines
7.3 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include "uart_pl011_registers.h"
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#include <am_mcu_apollo.h>
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#define PWRCTRL_MAX_WAIT_US 5
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static inline void pl011_ambiq_enable_clk(const struct device *dev)
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{
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get_uart(dev)->cr |= PL011_CR_AMBIQ_CLKEN;
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}
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static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk)
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{
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uint8_t clksel;
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switch (clk) {
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case 3000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_3MHZ;
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break;
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case 6000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_6MHZ;
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break;
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case 12000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_12MHZ;
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break;
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case 24000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_24MHZ;
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break;
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default:
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return -EINVAL;
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}
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get_uart(dev)->cr |= FIELD_PREP(PL011_CR_AMBIQ_CLKSEL, clksel);
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return 0;
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}
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static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk)
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{
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pl011_ambiq_enable_clk(dev);
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return pl011_ambiq_clk_set(dev, clk);
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}
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#ifdef CONFIG_PM_DEVICE
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/* Register status record.
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* The register status will be preserved to this variable before entering sleep mode,
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* and they will be restored after wake up.
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*/
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typedef struct {
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bool bValid;
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uint32_t regILPR;
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uint32_t regIBRD;
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uint32_t regFBRD;
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uint32_t regLCRH;
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uint32_t regCR;
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uint32_t regIFLS;
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uint32_t regIER;
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} uart_register_state_t;
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static uart_register_state_t sRegState[2];
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static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
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{
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int key;
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/*Uart module number*/
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uint32_t ui32Module = ((uint32_t)get_uart(dev) == UART0_BASE) ? 0 : 1;
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/*Uart Power module*/
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am_hal_pwrctrl_periph_e eUARTPowerModule =
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((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + ui32Module));
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/*Uart register status*/
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uart_register_state_t *pRegisterStatus = &sRegState[ui32Module];
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/* Decode the requested power state and update UART operation accordingly.*/
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switch (action) {
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/* Turn on the UART. */
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case PM_DEVICE_ACTION_RESUME:
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/* Make sure we don't try to restore an invalid state.*/
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if (!pRegisterStatus->bValid) {
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return -EPERM;
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}
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/*The resume and suspend actions may be executed back-to-back,
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* so we add a busy wait here for stabilization.
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*/
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k_busy_wait(100);
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/* Enable power control.*/
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am_hal_pwrctrl_periph_enable(eUARTPowerModule);
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/* Restore UART registers*/
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key = irq_lock();
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UARTn(ui32Module)->ILPR = pRegisterStatus->regILPR;
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UARTn(ui32Module)->IBRD = pRegisterStatus->regIBRD;
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UARTn(ui32Module)->FBRD = pRegisterStatus->regFBRD;
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UARTn(ui32Module)->LCRH = pRegisterStatus->regLCRH;
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UARTn(ui32Module)->CR = pRegisterStatus->regCR;
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UARTn(ui32Module)->IFLS = pRegisterStatus->regIFLS;
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UARTn(ui32Module)->IER = pRegisterStatus->regIER;
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pRegisterStatus->bValid = false;
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irq_unlock(key);
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return 0;
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case PM_DEVICE_ACTION_SUSPEND:
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while ((get_uart(dev)->fr & PL011_FR_BUSY) != 0)
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;
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/* Preserve UART registers*/
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key = irq_lock();
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pRegisterStatus->regILPR = UARTn(ui32Module)->ILPR;
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pRegisterStatus->regIBRD = UARTn(ui32Module)->IBRD;
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pRegisterStatus->regFBRD = UARTn(ui32Module)->FBRD;
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pRegisterStatus->regLCRH = UARTn(ui32Module)->LCRH;
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pRegisterStatus->regCR = UARTn(ui32Module)->CR;
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pRegisterStatus->regIFLS = UARTn(ui32Module)->IFLS;
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pRegisterStatus->regIER = UARTn(ui32Module)->IER;
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pRegisterStatus->bValid = true;
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irq_unlock(key);
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/* Clear all interrupts before sleeping as having a pending UART
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* interrupt burns power.
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*/
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UARTn(ui32Module)->IEC = 0xFFFFFFFF;
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/* If the user is going to sleep, certain bits of the CR register
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* need to be 0 to be low power and have the UART shut off.
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* Since the user either wishes to retain state which takes place
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* above or the user does not wish to retain state, it is acceptable
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* to set the entire CR register to 0.
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*/
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UARTn(ui32Module)->CR = 0;
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/* Disable power control.*/
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am_hal_pwrctrl_periph_disable(eUARTPowerModule);
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return 0;
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default:
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return -ENOTSUP;
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}
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}
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#endif /* CONFIG_PM_DEVICE */
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/* Problem: writes to power configure register takes some time to take effective.
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* Solution: Check device's power status to ensure that register has taken effective.
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* Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
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*/
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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#define DEVPWRSTATUS_OFFSET 0x10
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#define HCPA_MASK 0x4
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#define AMBIQ_UART_DEFINE(n) \
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PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
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static int pwr_on_ambiq_uart_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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while (!(sys_read32(pwr_status_addr) & HCPA_MASK)) { \
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}; \
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return 0; \
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} \
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static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
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{ \
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return clk_enable_ambiq_uart(dev, clk); \
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}
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#else
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#define DEVPWRSTATUS_OFFSET 0x4
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#define AMBIQ_UART_DEFINE(n) \
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PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
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static int pwr_on_ambiq_uart_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
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DT_INST_PHA(n, ambiq_pwrcfg, mask)) { \
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}; \
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return 0; \
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} \
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static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
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{ \
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return clk_enable_ambiq_uart(dev, clk); \
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */
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