36 lines
655 B
C
36 lines
655 B
C
/*
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* Copyright (c) 2017, 2023 NXP
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* Copyright (c) 2017, Phytec Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#include <zephyr/sys/util.h>
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#include <fsl_port.h>
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#if defined(CONFIG_SOC_MKW40Z4) || defined(CONFIG_SOC_MKW41Z4)
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#define LPUART0_CLK_SRC kCLOCK_CoreSysClk
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#endif
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#if defined(CONFIG_SOC_MKW22D5) || defined(CONFIG_SOC_MKW24D5)
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#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
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#endif
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#define PORT_MUX_GPIO kPORT_MuxAsGpio /* GPIO setting for the Port Mux Register */
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#ifndef _ASMLANGUAGE
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#include <fsl_common.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _SOC__H_ */
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