292 lines
6.5 KiB
C
292 lines
6.5 KiB
C
/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_spi0
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_sifive);
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#include "spi_sifive.h"
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#include <stdbool.h>
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/* Helper Functions */
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static inline void sys_set_mask(mem_addr_t addr, uint32_t mask, uint32_t value)
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{
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uint32_t temp = sys_read32(addr);
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temp &= ~(mask);
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temp |= value;
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sys_write32(temp, addr);
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}
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int spi_config(const struct device *dev, uint32_t frequency,
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uint16_t operation)
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{
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uint32_t div;
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uint32_t fmt_len;
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if (operation & SPI_HALF_DUPLEX) {
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return -ENOTSUP;
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}
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if (SPI_OP_MODE_GET(operation) != SPI_OP_MODE_MASTER) {
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return -ENOTSUP;
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}
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if (operation & SPI_MODE_LOOP) {
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return -ENOTSUP;
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}
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/* Set the SPI frequency */
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div = (SPI_CFG(dev)->f_sys / (frequency * 2U)) - 1;
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sys_write32((SF_SCKDIV_DIV_MASK & div), SPI_REG(dev, REG_SCKDIV));
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/* Set the polarity */
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if (operation & SPI_MODE_CPOL) {
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/* If CPOL is set, then SCK idles at logical 1 */
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sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
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} else {
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/* SCK idles at logical 0 */
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sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
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}
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/* Set the phase */
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if (operation & SPI_MODE_CPHA) {
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/*
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* If CPHA is set, then data is sampled
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* on the trailing SCK edge
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*/
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sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
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} else {
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/* Data is sampled on the leading SCK edge */
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sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
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}
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/* Get the frame length */
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fmt_len = SPI_WORD_SIZE_GET(operation);
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if (fmt_len > SF_FMT_LEN_MASK) {
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return -ENOTSUP;
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}
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/* Set the frame length */
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fmt_len = fmt_len << SF_FMT_LEN;
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fmt_len &= SF_FMT_LEN_MASK;
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sys_set_mask(SPI_REG(dev, REG_FMT), SF_FMT_LEN_MASK, fmt_len);
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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(operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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return -ENOTSUP;
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}
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/* Set single line operation */
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sys_set_mask(SPI_REG(dev, REG_FMT),
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SF_FMT_PROTO_MASK,
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SF_FMT_PROTO_SINGLE);
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/* Set the endianness */
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if (operation & SPI_TRANSFER_LSB) {
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sys_set_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
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} else {
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sys_clear_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
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}
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return 0;
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}
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void spi_sifive_send(const struct device *dev, uint16_t frame)
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{
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while (sys_read32(SPI_REG(dev, REG_TXDATA)) & SF_TXDATA_FULL) {
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}
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sys_write32((uint32_t) frame, SPI_REG(dev, REG_TXDATA));
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}
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uint16_t spi_sifive_recv(const struct device *dev)
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{
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uint32_t val;
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while ((val = sys_read32(SPI_REG(dev, REG_RXDATA))) & SF_RXDATA_EMPTY) {
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}
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return (uint16_t) val;
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}
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void spi_sifive_xfer(const struct device *dev, const bool hw_cs_control)
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{
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struct spi_context *ctx = &SPI_DATA(dev)->ctx;
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uint16_t txd, rxd;
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do {
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/* Send a frame */
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if (spi_context_tx_buf_on(ctx)) {
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txd = *ctx->tx_buf;
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} else {
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txd = 0U;
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}
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spi_sifive_send(dev, txd);
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spi_context_update_tx(ctx, 1, 1);
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/* Receive a frame */
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rxd = spi_sifive_recv(dev);
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if (spi_context_rx_buf_on(ctx)) {
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*ctx->rx_buf = rxd;
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}
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spi_context_update_rx(ctx, 1, 1);
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} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
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/* Deassert the CS line */
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if (!hw_cs_control) {
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spi_context_cs_control(&SPI_DATA(dev)->ctx, false);
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} else {
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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}
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spi_context_complete(ctx, 0);
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}
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/* API Functions */
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int spi_sifive_init(const struct device *dev)
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{
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int err;
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/* Disable SPI Flash mode */
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sys_clear_bit(SPI_REG(dev, REG_FCTRL), SF_FCTRL_EN);
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err = spi_context_cs_configure_all(&SPI_DATA(dev)->ctx);
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if (err < 0) {
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return err;
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}
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/* Make sure the context is unlocked */
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spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
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return 0;
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}
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int spi_sifive_transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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int rc = 0;
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bool hw_cs_control = false;
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/* Lock the SPI Context */
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spi_context_lock(&SPI_DATA(dev)->ctx, false, NULL, config);
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/* Configure the SPI bus */
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SPI_DATA(dev)->ctx.config = config;
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/*
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* If the chip select configuration is not present, we'll ask the
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* SPI peripheral itself to control the CS line
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*/
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if (config->cs == NULL) {
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hw_cs_control = true;
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}
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if (!hw_cs_control) {
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/*
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* If the user has requested manual GPIO control, ask the
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* context for control and disable HW control
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*/
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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} else {
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/*
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* Tell the hardware to control the requested CS pin.
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* NOTE:
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* For the SPI peripheral, the pin number is not the
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* GPIO pin, but the index into the list of available
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* CS lines for the SPI peripheral.
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*/
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sys_write32(config->slave, SPI_REG(dev, REG_CSID));
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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}
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rc = spi_config(dev, config->frequency, config->operation);
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if (rc < 0) {
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spi_context_release(&SPI_DATA(dev)->ctx, rc);
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return rc;
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}
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spi_context_buffers_setup(&SPI_DATA(dev)->ctx, tx_bufs, rx_bufs, 1);
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/* Assert the CS line */
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if (!hw_cs_control) {
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spi_context_cs_control(&SPI_DATA(dev)->ctx, true);
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} else {
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sys_write32(SF_CSMODE_HOLD, SPI_REG(dev, REG_CSMODE));
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}
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/* Perform transfer */
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spi_sifive_xfer(dev, hw_cs_control);
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rc = spi_context_wait_for_completion(&SPI_DATA(dev)->ctx);
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spi_context_release(&SPI_DATA(dev)->ctx, rc);
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return rc;
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}
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int spi_sifive_release(const struct device *dev,
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const struct spi_config *config)
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{
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spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
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return 0;
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}
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/* Device Instantiation */
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static struct spi_driver_api spi_sifive_api = {
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.transceive = spi_sifive_transceive,
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.release = spi_sifive_release,
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};
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#define SPI_INIT(n) \
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static struct spi_sifive_data spi_sifive_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_sifive_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_sifive_data_##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
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}; \
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static struct spi_sifive_cfg spi_sifive_cfg_##n = { \
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.base = DT_INST_REG_ADDR_BY_NAME(n, control), \
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.f_sys = DT_INST_PROP(n, clock_frequency), \
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}; \
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DEVICE_DT_INST_DEFINE(n, \
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spi_sifive_init, \
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NULL, \
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&spi_sifive_data_##n, \
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&spi_sifive_cfg_##n, \
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POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_sifive_api)
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#ifndef CONFIG_SIFIVE_SPI_0_ROM
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#if DT_INST_NODE_HAS_PROP(0, label)
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SPI_INIT(0);
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#endif /* DT_INST_NODE_HAS_PROP(0, label) */
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#endif /* !CONFIG_SIFIVE_SPI_0_ROM */
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#if DT_INST_NODE_HAS_PROP(1, label)
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SPI_INIT(1);
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#endif /* DT_INST_NODE_HAS_PROP(1, label) */
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#if DT_INST_NODE_HAS_PROP(2, label)
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SPI_INIT(2);
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#endif /* DT_INST_NODE_HAS_PROP(2, label) */
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