77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
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/* Control and Status Registers (CSRs) available for ZERO_RISCY. */
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#define ZERO_RISCY_MSTATUS 0x300U
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#define ZERO_RISCY_MTVEC 0x305U
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#define ZERO_RISCY_MEPC 0x341U
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#define ZERO_RISCY_MCAUSE 0x342U
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#define ZERO_RISCY_PCCR0 0x780U
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#define ZERO_RISCY_PCCR1 0x781U
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#define ZERO_RISCY_PCCR2 0x782U
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#define ZERO_RISCY_PCCR3 0x783U
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#define ZERO_RISCY_PCCR4 0x784U
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#define ZERO_RISCY_PCCR5 0x785U
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#define ZERO_RISCY_PCCR6 0x786U
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#define ZERO_RISCY_PCCR7 0x787U
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#define ZERO_RISCY_PCCR8 0x788U
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#define ZERO_RISCY_PCCR9 0x789U
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#define ZERO_RISCY_PCCR10 0x78AU
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#define ZERO_RISCY_PCCR 0x78BU
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#define ZERO_RISCY_PCER 0x7A0U
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#define ZERO_RISCY_PCMR 0x7A1U
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#define ZERO_RISCY_MHARTID 0xF14U
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/*
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* Map from SoC-specific configuration to generic Zephyr macros.
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*
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* These are expected by the code in arch/, and must be provided for
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* the kernel to work (or even build at all).
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*
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* Some of these may also apply to ZERO-RISCY; needs investigation.
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*/
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/*
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* MSTATUS CSR number. (Note this is the standard value in the RISC-V
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* privileged ISA v1.10).
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*/
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#define SOC_MSTATUS_REG ZERO_RISCY_MSTATUS
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/* MSTATUS's interrupt enable mask. This is also standard. */
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#define SOC_MSTATUS_IEN (1U << 3)
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/*
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* Exception code mask. Use of the bottom five bits is a subset of
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* what the standard allocates (which is XLEN-1 bits).
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*/
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#define SOC_MCAUSE_EXP_MASK 0x1F
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/*
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* Assembler instruction to exit from interrupt in machine mode.
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* The name "ERET" is a leftover from pre-v1.10 privileged ISA specs.
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* The "mret" mnemonic works properly with the Pulpino toolchain;
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* YMMV if using a generic toolchain.
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*/
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#define SOC_ERET mret
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/* The ecall exception number. This is a standard value. */
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#define SOC_MCAUSE_ECALL_EXP 11
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/*
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* Default MSTATUS value to write when scheduling in a new thread for
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* the first time.
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*
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* - Preserve machine privileges in MPP. If you see any documentation
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* telling you that MPP is read-only on this SoC, don't believe its
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* lies.
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* - Enable interrupts when exiting from exception into a new thread
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* by setting MPIE now, so it will be copied into IE on mret.
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*/
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#define ZERO_RISCY_MSTATUS_MPP_M (0x3U << 11)
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#define ZERO_RISCY_MSTATUS_MPIE_EN (1U << 7)
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#define SOC_MSTATUS_DEF_RESTORE (ZERO_RISCY_MSTATUS_MPP_M | \
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ZERO_RISCY_MSTATUS_MPIE_EN)
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ */
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