81 lines
2.1 KiB
YAML
81 lines
2.1 KiB
YAML
# Copyright 2018-2023, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP FlexSPI controller
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compatible: "nxp,imx-flexspi"
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include: [spi-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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ahb-bufferable:
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type: boolean
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description: |
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Enable AHB bufferable write access by setting register field
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AHBCR[BUFFERABLEEN].
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ahb-cacheable:
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type: boolean
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description: |
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Enable AHB cacheable read access by setting register field
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AHBCR[CACHEABLEEN].
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ahb-prefetch:
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type: boolean
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description: |
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Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
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ahb-read-addr-opt:
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type: boolean
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description: |
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Remove burst start address alignment limitation by setting register
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field AHBCR[READADDROPT].
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combination-mode:
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type: boolean
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description: |
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Combine port A and port B data pins to support octal mode access by
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setting register field MCR0[COMBINATIONEN].
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sck-differential-clock:
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type: boolean
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description: |
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Enable/disable SCKB pad use as SCKA differential clock output,
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when enabled, Port B flash access is not available.
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rx-clock-source:
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type: int
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default: 0
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enum:
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- 0 # Loopback internally
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- 1 # Loopback from DQS pad
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- 2 # Loopback from SCK pad
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- 3 # External input from DQS pad
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description: |
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Source clock for flash read. See the RXCLKSRC field in register MCR0.
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The default corresponds to the reset value of the register field.
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rx-buffer-config:
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type: array
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description: |
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Array of tuples to configure AHB RX buffers. Format is the following:
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<prefetch priority master_id buf_size>. Pass multiple tuples to configure
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multiple RX buffers (up to maximum supported by SOC).
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The tuple fields correspond to the following register bitfields:
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prefetch: AHBRXBUFxCRx[PREFETCH]
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priority: AHBRXBUFxCRx[PRIORITY]
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master_id: AHBRXBUFxCRx[MSTRID]
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buf_size: AHBRXBUFxCRx[BUFSZ]
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child-binding:
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description: NXP FlexSPI port
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include: nxp,imx-flexspi-device.yaml
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