92 lines
3.9 KiB
YAML
92 lines
3.9 KiB
YAML
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 DMA controller (V2)
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It is present on stm32 devices like stm32L4 or stm32WB.
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This DMA controller includes several channels with different requests.
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DMA clients connected to the STM32 DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each
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capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
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DMA clients connected to the STM32 DMA controller must use the format
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described in the dma.txt file, using a 3-cell specifier for each
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channel: a phandle to the DMA controller plus the following four integer cells:
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1. channel: the dma stream from 1 to <dma-requests>
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2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
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this value is 0 for Memory-to-memory transfers
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or a value between <1> .. <dma-generators> (not supported yet)
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or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>
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3. channel-config: A 32bit mask specifying the DMA channel configuration
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A name custom DMA flags for channel configuration is used
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which is device dependent see stm32_dma.h:
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-bit 5 : DMA cyclic mode config
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0x0: STM32_DMA_MODE_NORMAL
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0x1: STM32_DMA_MODE_CYCLIC
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-bit 6-7 : Direction (see dma.h)
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0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
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0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
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0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
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0x3: reserved for PERIPH to PERIPH
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-bit 9 : Peripheral Increment Address
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0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
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0x1: STM32_DMA_PERIPH_INC: increment address between transfers
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-bit 10 : Memory Increment Address
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0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
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0x1: STM32_DMA_MEM_INC: increment address between transfers
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-bit 11-12 : Peripheral data size
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0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
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0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
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0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
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0x3: reserved
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-bit 13-14 : Memory data size
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0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
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0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
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0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
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0x3: reserved
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-bit 15: Reserved
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-bit 16-17 : Priority level
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0x0: STM32_DMA_PRIORITY_LOW: low
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0x1: STM32_DMA_PRIORITY_MEDIUM: medium
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0x2: STM32_DMA_PRIORITY_HIGH: high
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0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
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Example of dma usual combination for peripheral transfer
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#define STM32_DMA_PERIPH_TX (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
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#define STM32_DMA_PERIPH_RX (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)
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Example of dma node for stm32wb55x
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dma2: dma-controller@40020400 {
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compatible = "st,stm32-dma-v2";
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...
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dma-requests = <7>;
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status = "disabled";
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};
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For the client part, example for stm32l476 on DMA1 instance
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Tx using channel 3 with request 1
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Rx using channel 2 with request 1
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spi1 {
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compatible = "st,stm32-spi";
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dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
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<&dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
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dma-names = "tx", "rx";
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};
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compatible: "st,stm32-dma-v2"
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include: st,stm32-dma.yaml
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properties:
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"#dma-cells":
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const: 3
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# Parameter syntax of stm32 follows the dma client dts syntax
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# in the Linux kernel declared in
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# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
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dma-cells:
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- channel
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- slot
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- channel-config
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