85 lines
2.4 KiB
YAML
85 lines
2.4 KiB
YAML
#
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# Copyright (c) 2023 Andes Technology Corporation.
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#
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# SPDX-License-Identifier: Apache-2.0
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compatible: "andestech,atcdmac300"
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include: dma-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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chain-transfer:
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type: int
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"#dma-cells":
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const: 3
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dma-cells:
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- channel
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- slot
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- channel-config
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description: |
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Andes DMA controller
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channel: a phandle to the DMA controller plus the following four integer cells:
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1. channel: the dma channel
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2. slot: DMA peripherial request ID
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3. channel-config: A 32bit mask specifying the DMA channel configuration
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which is device dependent:
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-bit 0-1 : Direction (see dma.h)
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0x0: MEM to MEM
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0x1: MEM to PERIPH
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0x2: PERIPH to MEM
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0x3: reserved for PERIPH to PERIPH
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-bit 2 : Peripheral Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 3 : Memory Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 4-6 : Peripheral data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: Double word (64 bits)
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0x4: Quad word (128 bits)
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0x5: Eight word (256 bits)
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0x6-0x7: reserved
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-bit 7-9 : Memory data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: Double word (64 bits)
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0x4: Quad word (128 bits)
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0x5: Eight word (256 bits)
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0x6-0x7: reserved
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-bit 10 : Priority level
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0x0: lower priority
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0x1: higher priority
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examples for andes_v5_ae350 DMA instance
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dma0: dma0@f0c00000 {
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compatible = "andestech,atcdmac300";
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...
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dma-channels = <8>;
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dma-requests = <16>;
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status = "disabled";
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label = "DMA_0";
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};
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For the client part, example for andes_ae350 DMA instance
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Tx using channel 2, slot 0
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Rx using channel 3, slot 1
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spi1: spi@f0f00000 {
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compatible = "andestech,atcspi200"
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dmas = <&dma0 2 0 0x0129>,
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<&dma0 3 1 0x012A>;
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dma-names = "tx", "rx";
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};
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