145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
/*
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* Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/arch/common/sys_bitops.h>
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#include <zephyr/drivers/clock_control/clock_agilex_ll.h>
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#include <socfpga_system_manager.h>
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/*
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* Intel SoC re-use Arm Trusted Firmware (ATF) driver code in Zephyr.
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* The migrated ATF driver code uses mmio_X macro to access the register.
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* The following macros map mmio_X to Zephyr compatible function for
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* register access. This allow Zephyr to re-use the ATF driver codes
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* without massive changes.
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*/
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#define mmio_write_32(addr, data) sys_write32((data), (addr))
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#define mmio_read_32(addr) sys_read32((addr))
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#define mmio_setbits_32(addr, mask) sys_set_bits((addr), (mask))
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#define mmio_clrbits_32(addr, mask) sys_clear_bits((addr), (mask))
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/* Extract reference clock from platform clock source */
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uint32_t get_ref_clk(uint32_t pllglob)
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{
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uint32_t arefclkdiv, ref_clk;
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uint32_t scr_reg;
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switch (CLKMGR_PSRC(pllglob)) {
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case CLKMGR_PLLGLOB_PSRC_EOSC1:
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scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
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ref_clk = mmio_read_32(scr_reg);
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break;
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case CLKMGR_PLLGLOB_PSRC_INTOSC:
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ref_clk = CLKMGR_INTOSC_HZ;
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break;
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case CLKMGR_PLLGLOB_PSRC_F2S:
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scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
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ref_clk = mmio_read_32(scr_reg);
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break;
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default:
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ref_clk = 0;
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break;
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}
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arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob);
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ref_clk /= arefclkdiv;
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return ref_clk;
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}
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/* Calculate clock frequency based on parameter */
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uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
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{
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uint32_t clk_psrc, mdiv, ref_clk;
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uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg;
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clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg);
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switch (CLKMGR_PSRC(clk_psrc)) {
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case CLKMGR_PSRC_MAIN:
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pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM;
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pllc_reg = CLKMGR_MAINPLL + main_pllc;
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pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
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break;
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case CLKMGR_PSRC_PER:
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pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM;
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pllc_reg = CLKMGR_PERPLL + per_pllc;
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pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB;
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break;
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default:
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return 0;
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}
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ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
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mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg));
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ref_clk *= mdiv;
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pllc_div = mmio_read_32(pllc_reg) & 0x7ff;
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return ref_clk / pllc_div;
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}
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/* Return L3 interconnect clock */
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uint32_t get_l3_clk(void)
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{
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uint32_t l3_clk;
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l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
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CLKMGR_PERPLL_PLLC1);
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return l3_clk;
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}
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/* Calculate clock frequency to be used for mpu */
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uint32_t get_mpu_clk(void)
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{
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uint32_t mpu_clk = 0;
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mpu_clk = get_clk_freq(CLKMGR_MAINPLL_MPUCLK, CLKMGR_MAINPLL_PLLC0,
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CLKMGR_PERPLL_PLLC0);
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return mpu_clk;
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}
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/* Calculate clock frequency to be used for watchdog timer */
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uint32_t get_wdt_clk(void)
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{
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uint32_t l3_clk, l4_sys_clk;
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l3_clk = get_l3_clk();
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l4_sys_clk = l3_clk / 4;
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return l4_sys_clk;
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}
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/* Calculate clock frequency to be used for UART driver */
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uint32_t get_uart_clk(void)
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{
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uint32_t data32, l3_clk, l4_sp_clk;
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l3_clk = get_l3_clk();
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data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV);
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data32 = (data32 >> 16) & 0x3;
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l4_sp_clk = l3_clk >> data32;
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return l4_sp_clk;
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}
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/* Calculate clock frequency to be used for SDMMC driver */
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uint32_t get_mmc_clk(void)
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{
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uint32_t data32, mmc_clk;
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mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR,
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CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3);
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data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR);
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data32 = (data32 & 0x7ff) + 1;
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mmc_clk = (mmc_clk / data32) / 4;
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return mmc_clk;
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}
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