686 lines
14 KiB
C
686 lines
14 KiB
C
/*
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* Copyright (c) 2017-2018 ARM Limited
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT smsc_lan9220
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/* SMSC911x/SMSC9220 driver. Partly based on mbedOS driver. */
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#define LOG_MODULE_NAME eth_smsc911x
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include <soc.h>
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#include <device.h>
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#include <errno.h>
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#include <init.h>
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#include <kernel.h>
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#include <sys/__assert.h>
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#include <net/net_core.h>
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#include <net/net_pkt.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/sys_io.h>
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#include <net/ethernet.h>
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#include "ethernet/eth_stats.h"
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#ifdef CONFIG_SHARED_IRQ
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#include <shared_irq.h>
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#endif
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#include "eth_smsc911x_priv.h"
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#define RESET_TIMEOUT 10
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#define PHY_RESET_TIMEOUT K_MSEC(100)
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#define REG_WRITE_TIMEOUT 50
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/* Controller has only one PHY with address 1 */
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#define PHY_ADDR 1
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struct eth_context {
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struct net_if *iface;
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uint8_t mac[6];
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#if defined(CONFIG_NET_STATISTICS_ETHERNET)
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struct net_stats_eth stats;
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#endif
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};
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/* SMSC911x helper functions */
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static int smsc_mac_regread(uint8_t reg, uint32_t *val)
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{
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uint32_t cmd = MAC_CSR_CMD_BUSY | MAC_CSR_CMD_READ | reg;
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SMSC9220->MAC_CSR_CMD = cmd;
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while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {
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}
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*val = SMSC9220->MAC_CSR_DATA;
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return 0;
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}
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static int smsc_mac_regwrite(uint8_t reg, uint32_t val)
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{
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uint32_t cmd = MAC_CSR_CMD_BUSY | MAC_CSR_CMD_WRITE | reg;
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SMSC9220->MAC_CSR_DATA = val;
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SMSC9220->MAC_CSR_CMD = cmd;
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while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {
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}
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return 0;
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}
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int smsc_phy_regread(uint8_t regoffset, uint32_t *data)
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{
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uint32_t val = 0U;
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uint32_t phycmd = 0U;
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unsigned int time_out = REG_WRITE_TIMEOUT;
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if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &val) < 0) {
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return -1;
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}
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if (val & MAC_MII_ACC_MIIBZY) {
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*data = 0U;
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return -EBUSY;
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}
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phycmd = 0U;
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phycmd |= PHY_ADDR << 11;
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phycmd |= (regoffset & 0x1F) << 6;
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phycmd |= MAC_MII_ACC_READ;
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phycmd |= MAC_MII_ACC_MIIBZY; /* Operation start */
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if (smsc_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd)) {
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return -1;
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}
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val = 0U;
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do {
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k_sleep(K_MSEC(1));
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time_out--;
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if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &val)) {
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return -1;
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}
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} while (time_out != 0U && (val & MAC_MII_ACC_MIIBZY));
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if (time_out == 0U) {
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return -ETIMEDOUT;
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}
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if (smsc_mac_regread(SMSC9220_MAC_MII_DATA, data) < 0) {
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return -1;
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}
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return 0;
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}
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int smsc_phy_regwrite(uint8_t regoffset, uint32_t data)
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{
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uint32_t val = 0U;
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uint32_t phycmd = 0U;
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unsigned int time_out = REG_WRITE_TIMEOUT;
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if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &val) < 0) {
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return -1;
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}
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if (val & MAC_MII_ACC_MIIBZY) {
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return -EBUSY;
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}
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if (smsc_mac_regwrite(SMSC9220_MAC_MII_DATA, data & 0xFFFF) < 0) {
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return -1;
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}
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phycmd |= PHY_ADDR << 11;
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phycmd |= (regoffset & 0x1F) << 6;
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phycmd |= MAC_MII_ACC_WRITE;
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phycmd |= MAC_MII_ACC_MIIBZY; /* Operation start */
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if (smsc_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd) < 0) {
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return -1;
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}
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do {
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k_sleep(K_MSEC(1));
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time_out--;
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if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd)) {
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return -1;
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}
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} while (time_out != 0U && (phycmd & MAC_MII_ACC_MIIBZY));
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if (time_out == 0U) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int smsc_read_mac_address(uint8_t *mac)
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{
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uint32_t tmp;
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int res;
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res = smsc_mac_regread(SMSC9220_MAC_ADDRL, &tmp);
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if (res < 0) {
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return res;
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}
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mac[0] = (uint8_t)(tmp >> 0);
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mac[1] = (uint8_t)(tmp >> 8);
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mac[2] = (uint8_t)(tmp >> 16);
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mac[3] = (uint8_t)(tmp >> 24);
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res = smsc_mac_regread(SMSC9220_MAC_ADDRH, &tmp);
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if (res < 0) {
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return res;
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}
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mac[4] = (uint8_t)(tmp >> 0);
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mac[5] = (uint8_t)(tmp >> 8);
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return 0;
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}
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static int smsc_check_id(void)
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{
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uint32_t id = SMSC9220->ID_REV;
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/* If bottom and top halves of the word are the same,
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* the hardware is (likely) not present.
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*/
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if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
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return -1;
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}
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switch (((id >> 16) & 0xFFFF)) {
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case 0x9220: /* SMSC9220 on MPS2 */
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case 0x0118: /* SMS9118 as emulated by QEMU */
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break;
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default:
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return -1;
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}
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return 0;
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}
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static int smsc_soft_reset(void)
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{
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unsigned int time_out = RESET_TIMEOUT;
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SMSC9220->HW_CFG |= HW_CFG_SRST;
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do {
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k_sleep(K_MSEC(1));
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time_out--;
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} while (time_out != 0U && (SMSC9220->HW_CFG & HW_CFG_SRST));
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if (time_out == 0U) {
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return -1;
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}
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return 0;
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}
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void smsc_set_txfifo(unsigned int val)
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{
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/* 2kb minimum, 14kb maximum */
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if (val >= 2U && val <= 14U) {
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SMSC9220->HW_CFG = val << 16;
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}
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}
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void smsc_init_irqs(void)
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{
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SMSC9220->INT_EN = 0;
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/* Clear all interrupts */
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SMSC9220->INT_STS = 0xFFFFFFFF;
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/* Polarity config which works with QEMU */
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/* IRQ deassertion at 220 usecs and master IRQ enable */
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SMSC9220->IRQ_CFG = 0x22000111;
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}
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static int smsc_check_phy(void)
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{
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uint32_t phyid1, phyid2;
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if (smsc_phy_regread(SMSC9220_PHY_ID1, &phyid1)) {
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return -1;
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}
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if (smsc_phy_regread(SMSC9220_PHY_ID2, &phyid2)) {
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return -1;
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}
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return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
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(phyid1 == 0x0 && phyid2 == 0x0));
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}
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int smsc_reset_phy(void)
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{
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uint32_t val;
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if (smsc_phy_regread(SMSC9220_PHY_BCONTROL, &val)) {
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return -1;
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}
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val |= 1 << 15;
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if (smsc_phy_regwrite(SMSC9220_PHY_BCONTROL, val)) {
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return -1;
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}
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return 0;
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}
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/**
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* Advertise all speeds and pause capabilities
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*/
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void smsc_advertise_caps(void)
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{
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uint32_t aneg_adv = 0U;
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smsc_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
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aneg_adv |= 0xDE0;
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smsc_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
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smsc_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
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}
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void smsc_establish_link(void)
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{
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uint32_t bcr = 0U;
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uint32_t hw_cfg = 0U;
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smsc_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
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bcr |= (1 << 12) | (1 << 9);
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smsc_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
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smsc_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
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hw_cfg = SMSC9220->HW_CFG;
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hw_cfg &= 0xF0000;
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hw_cfg |= (1 << 20);
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SMSC9220->HW_CFG = hw_cfg;
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}
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static inline void smsc_enable_xmit(void)
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{
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SMSC9220->TX_CFG = 0x2 /*TX_CFG_TX_ON*/;
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}
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void smsc_enable_mac_xmit(void)
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{
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uint32_t mac_cr = 0U;
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smsc_mac_regread(SMSC9220_MAC_CR, &mac_cr);
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mac_cr |= (1 << 3); /* xmit enable */
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mac_cr |= (1 << 28); /* Heartbeat disable */
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smsc_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
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}
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void smsc_enable_mac_recv(void)
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{
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uint32_t mac_cr = 0U;
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smsc_mac_regread(SMSC9220_MAC_CR, &mac_cr);
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mac_cr |= (1 << 2); /* Recv enable */
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smsc_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
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}
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int smsc_init(void)
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{
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unsigned int phyreset = 0U;
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if (smsc_check_id() < 0) {
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return -1;
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}
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if (smsc_soft_reset() < 0) {
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return -1;
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}
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smsc_set_txfifo(5);
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/* Sets automatic flow control thresholds, and backpressure */
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/* threshold to defaults specified. */
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SMSC9220->AFC_CFG = 0x006E3740;
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/* May need to initialize EEPROM/read MAC from it on real HW. */
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/* Configure GPIOs as LED outputs. */
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SMSC9220->GPIO_CFG = 0x70070000;
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smsc_init_irqs();
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/* Configure MAC addresses here if needed. */
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if (smsc_check_phy() < 0) {
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return -1;
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}
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if (smsc_reset_phy() < 0) {
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return -1;
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}
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k_sleep(PHY_RESET_TIMEOUT);
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/* Checking whether phy reset completed successfully.*/
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if (smsc_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset)) {
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return 1;
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}
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if (phyreset & (1 << 15)) {
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return 1;
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}
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smsc_advertise_caps();
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/* bit [12] of BCONTROL seems self-clearing. */
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/* Although it's not so in the manual. */
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smsc_establish_link();
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/* Interrupt threshold */
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SMSC9220->FIFO_INT = 0xFF000000;
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smsc_enable_mac_xmit();
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smsc_enable_xmit();
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SMSC9220->RX_CFG = 0;
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smsc_enable_mac_recv();
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/* Rx status FIFO level irq threshold */
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SMSC9220->FIFO_INT &= ~(0xFF); /* Clear 2 bottom nibbles */
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/* This sleep is compulsory otherwise txmit/receive will fail. */
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k_sleep(K_MSEC(2000));
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return 0;
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}
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/* Driver functions */
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static enum ethernet_hw_caps eth_smsc911x_get_capabilities(struct device *dev)
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{
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ARG_UNUSED(dev);
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return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T;
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}
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#if defined(CONFIG_NET_STATISTICS_ETHERNET)
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static struct net_stats_eth *get_stats(struct device *dev)
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{
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struct eth_context *context = dev->driver_data;
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return &context->stats;
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}
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#endif
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static void eth_initialize(struct net_if *iface)
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{
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struct device *dev = net_if_get_device(iface);
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struct eth_context *context = dev->driver_data;
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LOG_DBG("eth_initialize");
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smsc_read_mac_address(context->mac);
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SMSC9220->INT_EN |= BIT(SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL);
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net_if_set_link_addr(iface, context->mac, sizeof(context->mac),
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NET_LINK_ETHERNET);
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context->iface = iface;
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ethernet_init(iface);
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}
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static int smsc_write_tx_fifo(const uint8_t *buf, uint32_t len, bool is_last)
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{
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uint32_t *buf32;
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__ASSERT_NO_MSG(((uintptr_t)buf & 3) == 0);
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if (is_last) {
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/* Last fragment may be not full */
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len = (len + 3) & ~3;
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}
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if ((len & 3) != 0U || len == 0U) {
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LOG_ERR("Chunk size not aligned: %u", len);
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return -1;
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}
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buf32 = (uint32_t *)buf;
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len /= 4U;
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do {
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SMSC9220->TX_DATA_PORT = *buf32++;
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} while (--len);
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return 0;
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}
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static int eth_tx(struct device *dev, struct net_pkt *pkt)
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{
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uint16_t total_len = net_pkt_get_len(pkt);
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static uint8_t tx_buf[NET_ETH_MAX_FRAME_SIZE] __aligned(4);
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uint32_t txcmd_a, txcmd_b;
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uint32_t tx_stat;
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int res;
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txcmd_a = (1/*is_first_segment*/ << 13) | (1/*is_last_segment*/ << 12)
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| total_len;
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/* Use len as a tag */
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txcmd_b = total_len << 16 | total_len;
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SMSC9220->TX_DATA_PORT = txcmd_a;
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SMSC9220->TX_DATA_PORT = txcmd_b;
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if (net_pkt_read(pkt, tx_buf, total_len)) {
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goto error;
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}
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res = smsc_write_tx_fifo(tx_buf, total_len, true);
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if (res < 0) {
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goto error;
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}
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tx_stat = SMSC9220->TX_STAT_PORT;
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LOG_DBG("TX_STAT: %x", tx_stat);
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return 0;
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error:
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LOG_ERR("Writing pkt to FIFO failed");
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return -1;
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}
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static const struct ethernet_api api_funcs = {
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.iface_api.init = eth_initialize,
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.get_capabilities = eth_smsc911x_get_capabilities,
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.send = eth_tx,
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#if defined(CONFIG_NET_STATISTICS_ETHERNET)
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.get_stats = get_stats,
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#endif
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};
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static void smsc_discard_pkt(void)
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{
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/* TODO: */
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/* Datasheet p.43: */
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/* When performing a fast-forward, there must be at least 4 DWORDs
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* of data in the RX data FIFO for the packet being discarded. For
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* less than 4 DWORDs do not use RX_FFWD. In this case data must be
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* read from the RX data FIFO and discarded using standard PIO read
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* operations.
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*/
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SMSC9220->RX_DP_CTRL = RX_DP_CTRL_RX_FFWD;
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}
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static inline void smsc_wait_discard_pkt(void)
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{
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while ((SMSC9220->RX_DP_CTRL & RX_DP_CTRL_RX_FFWD) != 0) {
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}
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}
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static int smsc_read_rx_fifo(struct net_pkt *pkt, uint32_t len)
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{
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uint32_t buf32;
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__ASSERT_NO_MSG((len & 3) == 0U && len >= 4U);
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len /= 4U;
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do {
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buf32 = SMSC9220->RX_DATA_PORT;
|
|
|
|
if (net_pkt_write(pkt, &buf32, sizeof(uint32_t))) {
|
|
return -1;
|
|
}
|
|
} while (--len);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct net_pkt *smsc_recv_pkt(struct device *dev, uint32_t pkt_size)
|
|
{
|
|
struct eth_context *context = dev->driver_data;
|
|
struct net_pkt *pkt;
|
|
uint32_t rem_size;
|
|
|
|
/* Round up to next DWORD size */
|
|
rem_size = (pkt_size + 3) & ~3;
|
|
/* Don't account for FCS when filling net pkt */
|
|
rem_size -= 4U;
|
|
|
|
pkt = net_pkt_rx_alloc_with_buffer(context->iface, rem_size,
|
|
AF_UNSPEC, 0, K_NO_WAIT);
|
|
if (!pkt) {
|
|
LOG_ERR("Failed to obtain RX buffer");
|
|
smsc_discard_pkt();
|
|
return NULL;
|
|
}
|
|
|
|
if (smsc_read_rx_fifo(pkt, rem_size) < 0) {
|
|
smsc_discard_pkt();
|
|
net_pkt_unref(pkt);
|
|
return NULL;
|
|
}
|
|
|
|
/* Discard FCS */
|
|
{
|
|
uint32_t __unused dummy = SMSC9220->RX_DATA_PORT;
|
|
}
|
|
|
|
/* Adjust len of the last buf down for DWORD alignment */
|
|
if (pkt_size & 3) {
|
|
net_pkt_update_length(pkt, net_pkt_get_len(pkt) -
|
|
(4 - (pkt_size & 3)));
|
|
}
|
|
|
|
return pkt;
|
|
}
|
|
|
|
static void eth_smsc911x_isr(struct device *dev)
|
|
{
|
|
uint32_t int_status = SMSC9220->INT_STS;
|
|
struct eth_context *context = dev->driver_data;
|
|
|
|
LOG_DBG("%s: INT_STS=%x INT_EN=%x", __func__,
|
|
int_status, SMSC9220->INT_EN);
|
|
|
|
if (int_status & BIT(SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL)) {
|
|
struct net_pkt *pkt;
|
|
uint32_t pkt_size, val;
|
|
uint32_t rx_stat;
|
|
|
|
val = SMSC9220->RX_FIFO_INF;
|
|
uint32_t pkt_pending = BFIELD(val, RX_FIFO_INF_RXSUSED);
|
|
|
|
LOG_DBG("in RX FIFO: pkts: %u, bytes: %u",
|
|
pkt_pending,
|
|
BFIELD(val, RX_FIFO_INF_RXDUSED));
|
|
|
|
/* Ack rxstatus_fifo_level only when no packets pending. The
|
|
* idea is to serve 1 packet per interrupt (e.g. to allow
|
|
* higher priority interrupts to fire) by keeping interrupt
|
|
* pending for as long as there're packets in FIFO. And when
|
|
* there's none, finally acknowledge it.
|
|
*/
|
|
if (pkt_pending == 0U) {
|
|
goto done;
|
|
}
|
|
|
|
int_status &= ~BIT(SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL);
|
|
|
|
/* Make sure that any previously started discard op is
|
|
* finished.
|
|
*/
|
|
smsc_wait_discard_pkt();
|
|
|
|
rx_stat = SMSC9220->RX_STAT_PORT;
|
|
pkt_size = BFIELD(rx_stat, RX_STAT_PORT_PKT_LEN);
|
|
LOG_DBG("pkt sz: %u", pkt_size);
|
|
|
|
pkt = smsc_recv_pkt(dev, pkt_size);
|
|
|
|
LOG_DBG("out RX FIFO: pkts: %u, bytes: %u",
|
|
SMSC9220_BFIELD(RX_FIFO_INF, RXSUSED),
|
|
SMSC9220_BFIELD(RX_FIFO_INF, RXDUSED));
|
|
|
|
if (pkt != NULL) {
|
|
int res = net_recv_data(context->iface, pkt);
|
|
|
|
if (res < 0) {
|
|
LOG_ERR("net_recv_data: %d", res);
|
|
net_pkt_unref(pkt);
|
|
}
|
|
}
|
|
}
|
|
|
|
done:
|
|
/* Ack pending interrupts */
|
|
SMSC9220->INT_STS = int_status;
|
|
|
|
}
|
|
|
|
/* Bindings to the platform */
|
|
|
|
DEVICE_DECLARE(eth_smsc911x_0);
|
|
|
|
int eth_init(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(0),
|
|
DT_INST_IRQ(0, priority),
|
|
eth_smsc911x_isr, DEVICE_GET(eth_smsc911x_0), 0);
|
|
|
|
int ret = smsc_init();
|
|
|
|
if (ret != 0) {
|
|
LOG_ERR("smsc911x failed to initialize");
|
|
return -ENODEV;
|
|
}
|
|
|
|
irq_enable(DT_INST_IRQN(0));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct eth_context eth_0_context;
|
|
|
|
ETH_NET_DEVICE_INIT(eth_smsc911x_0, "smsc911x_0",
|
|
eth_init, device_pm_control_nop, ð_0_context,
|
|
NULL /*ð_config_0*/, CONFIG_ETH_INIT_PRIORITY, &api_funcs,
|
|
NET_ETH_MTU /*MTU*/);
|