245 lines
7.0 KiB
C
245 lines
7.0 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include "soc.h"
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
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#include <xtensa/config/core-isa.h>
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#include <xtensa/corebits.h>
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#include <zephyr/kernel_structs.h>
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#include <string.h>
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#include <zephyr/toolchain/gcc.h>
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#include <zephyr/types.h>
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#include <zephyr/linker/linker-defs.h>
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#include <kernel_internal.h>
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#include <zephyr/sys/util.h>
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#include "esp_private/system_internal.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/rtc.h"
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#include "soc/syscon_reg.h"
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#include "hal/soc_ll.h"
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#include "hal/wdt_hal.h"
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#include "soc/cpu.h"
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#include "soc/gpio_periph.h"
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#include "esp_spi_flash.h"
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#include "esp_err.h"
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#include "esp_timer.h"
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#include "esp_app_format.h"
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#include "esp_clk_internal.h"
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#ifdef CONFIG_MCUBOOT
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#include "bootloader_init.h"
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#endif /* CONFIG_MCUBOOT */
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#include <zephyr/sys/printk.h>
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extern void z_cstart(void);
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#ifndef CONFIG_MCUBOOT
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/*
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* This function is a container for SoC patches
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* that needs to be applied during the startup.
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*/
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static void IRAM_ATTR esp_errata(void)
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{
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/* Handle the clock gating fix */
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
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* signals to ensure that the App core stops running in single-core mode.
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*/
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
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/* Handle the Dcache case following the IDF startup code */
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#if CONFIG_ESP32S3_DATA_CACHE_16KB
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Cache_Invalidate_DCache_All();
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Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
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#endif
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}
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#endif /* CONFIG_MCUBOOT */
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/*
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* This is written in C rather than assembly since, during the port bring up,
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* Zephyr is being booted by the Espressif bootloader. With it, the C stack
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* is already set up.
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*/
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void IRAM_ATTR __esp_platform_start(void)
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{
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extern uint32_t _init_start;
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/* Move the exception vector table to IRAM. */
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__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
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z_bss_zero();
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/* Disable normal interrupts. */
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__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
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/* Initialize the architecture CPU pointer. Some of the
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* initialization code wants a valid _current before
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* arch_kernel_init() is invoked.
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*/
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
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#ifdef CONFIG_MCUBOOT
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/* MCUboot early initialisation. */
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if (bootloader_init()) {
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abort();
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}
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#else
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/* Configure the mode of instruction cache : cache size, cache line size. */
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esp_config_instruction_cache_mode();
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/* If we need use SPIRAM, we should use data cache.
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* Configure the mode of data : cache size, cache line size.
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*/
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esp_config_data_cache_mode();
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/* Apply SoC patches */
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esp_errata();
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/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence
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* related issues in application. Hence disable that as we are about to start
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* Zephyr environment.
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*/
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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esp_clk_init();
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esp_timer_early_init();
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#if CONFIG_SOC_FLASH_ESP32
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spi_flash_guard_set(&g_flash_guard_default_ops);
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#endif
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#endif /* CONFIG_MCUBOOT */
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esp_intr_initialize();
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/* Start Zephyr */
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z_cstart();
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CODE_UNREACHABLE;
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}
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/* Boot-time static default printk handler, possibly to be overridden later. */
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int IRAM_ATTR arch_printk_char_out(int c)
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{
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if (c == '\n') {
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esp_rom_uart_tx_one_char('\r');
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}
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esp_rom_uart_tx_one_char(c);
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return 0;
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}
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void sys_arch_reboot(int type)
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{
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esp_restart_noos();
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}
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void IRAM_ATTR esp_restart_noos(void)
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{
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/* disable interrupts */
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z_xt_ints_off(0xFFFFFFFF);
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/* enable RTC watchdog for 1 second */
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wdt_hal_context_t wdt_ctx;
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uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false);
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wdt_hal_write_protect_disable(&wdt_ctx);
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wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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/* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */
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wdt_hal_set_flashboot_en(&wdt_ctx, true);
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wdt_hal_write_protect_enable(&wdt_ctx);
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/* disable TG0/TG1 watchdogs */
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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/* Flush any data left in UART FIFOs */
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esp_rom_uart_tx_wait_idle(0);
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esp_rom_uart_tx_wait_idle(1);
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esp_rom_uart_tx_wait_idle(2);
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/* Disable cache */
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Cache_Disable_ICache();
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Cache_Disable_DCache();
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const uint32_t core_id = cpu_hal_get_core_id();
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#if CONFIG_SMP
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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soc_ll_reset_core(other_core_id);
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soc_ll_stall_core(other_core_id);
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#endif
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/* 2nd stage bootloader reconfigures SPI flash signals. */
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/* Reset them to the defaults expected by ROM */
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
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SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
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SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST |
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SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST |
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SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST);
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REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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/* Reset timer/spi/uart */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST |
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SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
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/* Reset DMA */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
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SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
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CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
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rtc_clk_cpu_freq_set_xtal();
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/* Reset CPUs */
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if (core_id == 0) {
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/* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */
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soc_ll_reset_core(1);
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soc_ll_reset_core(0);
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} else {
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/* Running on APP CPU: need to reset PRO CPU and unstall it, */
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/* then reset APP CPU */
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soc_ll_reset_core(0);
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soc_ll_stall_core(0);
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soc_ll_reset_core(1);
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}
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while (true) {
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;
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}
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}
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