181 lines
5.6 KiB
C
181 lines
5.6 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_UART_H
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#define _MEC_UART_H
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#include <stdint.h>
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#include <stddef.h>
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#define MCHP_UART_RX_FIFO_MAX_LEN 16u
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#define MCHP_UART_TX_FIFO_MAX_LEN 16u
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#define MCHP_UART_BAUD_RATE_MIN 50u
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#define MCHP_UART_BAUD_RATE_MAX 1500000u
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#define MCHP_UART_SPACING 0x400u
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/*
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* LCR DLAB=0
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* Transmit buffer(WO), Receive buffer(RO)
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* LCR DLAB=1, BAUD rate divisor LSB
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*/
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#define MCHP_UART_RTXB_OFS 0u
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#define MCHP_UART_BRGD_LSB_OFS 0u
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/*
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* LCR DLAB=0
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* Interrupt Enable Register, R/W
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* LCR DLAB=1, BAUD rate divisor MSB
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*/
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#define MCHP_UART_BRGD_MSB_OFS 1u
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#define MCHP_UART_IER_OFS 1u
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#define MCHP_UART_IER_MASK 0x0fu
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#define MCHP_UART_IER_ERDAI 0x01u /* Received data available and timeouts */
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#define MCHP_UART_IER_ETHREI 0x02u /* TX Holding register empty */
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#define MCHP_UART_IER_ELSI 0x04u /* Errors: Overrun, Parity, Framing, and Break */
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#define MCHP_UART_IER_EMSI 0x08u /* Modem Status */
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#define MCHP_UART_IER_ALL 0x0fu
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/* FIFO Control Register, Write-Only */
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#define MCHP_UART_FCR_OFS 2u
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#define MCHP_UART_FCR_MASK 0xcfu
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#define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */
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#define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */
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#define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
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#define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */
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#define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xc0u /* RX FIFO trigger level mask */
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#define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u
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#define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u
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#define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u
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#define MCHP_UART_FCR_RX_FIFO_LVL_14 0xc0u
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/* Interrupt Identification Register, Read-Only */
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#define MCHP_UART_IIR_OFS 2u
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#define MCHP_UART_IIR_MASK 0xcfu
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#define MCHP_UART_IIR_NOT_IPEND 0x01u
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#define MCHP_UART_IIR_INTID_MASK0 0x07u
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#define MCHP_UART_IIR_INTID_POS 1u
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#define MCHP_UART_IIR_INTID_MASK 0x0eu
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#define MCHP_UART_IIR_FIFO_EN_MASK 0xc0u
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/*
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* interrupt values
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* Highest priority: Line status, overrun, framing, or break
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* Highest-1. RX data available or RX FIFO trigger level reached
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* Highest-2. RX timeout
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* Highest-3. TX Holding register empty
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* Highest-4. MODEM status
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*/
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#define MCHP_UART_IIR_INT_NONE 0x01u
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#define MCHP_UART_IIR_INT_LS 0x06u
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#define MCHP_UART_IIR_INT_RX 0x04u
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#define MCHP_UART_IIR_INT_RX_TMOUT 0x0cu
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#define MCHP_UART_IIR_INT_THRE 0x02u
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#define MCHP_UART_IIR_INT_MS 0x00u
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/* Line Control Register R/W */
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#define MCHP_UART_LCR_OFS 3u
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#define MCHP_UART_LCR_WORD_LEN_MASK 0x03u
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#define MCHP_UART_LCR_WORD_LEN_5 0x00u
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#define MCHP_UART_LCR_WORD_LEN_6 0x01u
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#define MCHP_UART_LCR_WORD_LEN_7 0x02u
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#define MCHP_UART_LCR_WORD_LEN_8 0x03u
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#define MCHP_UART_LCR_STOP_BIT_1 0x00u
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#define MCHP_UART_LCR_STOP_BIT_2 0x04u
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#define MCHP_UART_LCR_PARITY_NONE 0x00u
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#define MCHP_UART_LCR_PARITY_EN 0x08u
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#define MCHP_UART_LCR_PARITY_ODD 0x00u
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#define MCHP_UART_LCR_PARITY_EVEN 0x10u
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#define MCHP_UART_LCR_STICK_PARITY 0x20u
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#define MCHP_UART_LCR_BREAK_EN 0x40u
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#define MCHP_UART_LCR_DLAB_EN 0x80u
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/* MODEM Control Register R/W */
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#define MCHP_UART_MCR_OFS 4u
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#define MCHP_UART_MCR_MASK 0x1fu
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#define MCHP_UART_MCR_DTRn 0x01u
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#define MCHP_UART_MCR_RTSn 0x02u
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#define MCHP_UART_MCR_OUT1 0x04u
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#define MCHP_UART_MCR_OUT2 0x08u
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#define MCHP_UART_MCR_LOOPBCK_EN 0x10u
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/* Line Status Register RO */
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#define MCHP_UART_LSR_OFS 5u
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#define MCHP_UART_LSR_DATA_RDY 0x01u
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#define MCHP_UART_LSR_OVERRUN 0x02u
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#define MCHP_UART_LSR_PARITY 0x04u
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#define MCHP_UART_LSR_FRAME 0x08u
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#define MCHP_UART_LSR_RX_BREAK 0x10u
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#define MCHP_UART_LSR_THRE 0x20u
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#define MCHP_UART_LSR_TEMT 0x40u
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#define MCHP_UART_LSR_FIFO_ERR 0x80u
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#define MCHP_UART_LSR_ANY 0xffu
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/* MODEM Status Register RO */
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#define MCHP_UART_MSR_OFS 6u
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#define MCHP_UART_MSR_DCTS 0x01u
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#define MCHP_UART_MSR_DDSR 0x02u
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#define MCHP_UART_MSR_TERI 0x04u
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#define MCHP_UART_MSR_DDCD 0x08u
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#define MCHP_UART_MSR_CTS 0x10u
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#define MCHP_UART_MSR_DSR 0x20u
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#define MCHP_UART_MSR_RI 0x40u
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#define MCHP_UART_MSR_DCD 0x80u
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/* Scratch Register RO */
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#define MCHP_UART_SCR_OFS 7u
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/* UART Logical Device Activate Register */
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#define MCHP_UART_LD_ACT_OFS 0x330u
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#define MCHP_UART_LD_ACTIVATE 0x01u
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/* UART Logical Device Config Register */
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#define MCHP_UART_LD_CFG_OFS 0x3f0u
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#define MCHP_UART_LD_CFG_INTCLK 0u
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#define MCHP_UART_LD_CFG_NO_INVERT 0u
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#define MCHP_UART_LD_CFG_RESET_SYS 0u
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#define MCHP_UART_LD_CFG_EXTCLK BIT(0)
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#define MCHP_UART_LD_CFG_RESET_VCC BIT(1)
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#define MCHP_UART_LD_CFG_INVERT BIT(2)
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/* BAUD rate generator */
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#define MCHP_UART_INT_CLK_24M BIT(15)
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/* 1.8MHz internal clock source */
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#define MCHP_UART_1P8M_BAUD_50 2304u
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#define MCHP_UART_1P8M_BAUD_110 1536u
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#define MCHP_UART_1P8M_BAUD_150 768u
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#define MCHP_UART_1P8M_BAUD_300 384u
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#define MCHP_UART_1P8M_BAUD_1200 96u
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#define MCHP_UART_1P8M_BAUD_2400 48u
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#define MCHP_UART_1P8M_BAUD_9600 12u
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#define MCHP_UART_1P8M_BAUD_19200 6u
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#define MCHP_UART_1P8M_BAUD_38400 3u
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#define MCHP_UART_1P8M_BAUD_57600 2u
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#define MCHP_UART_1P8M_BAUD_115200 1u
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/* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */
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#define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M))
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#define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M))
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/** @brief 16550 compatible UART. Size = 1012(0x3f4) */
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struct uart_regs {
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volatile uint8_t RTXB;
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volatile uint8_t IER;
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volatile uint8_t IIR_FCR;
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volatile uint8_t LCR;
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volatile uint8_t MCR;
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volatile uint8_t LSR;
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volatile uint8_t MSR;
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volatile uint8_t SCR;
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uint8_t RSVDA[0x330 - 0x08];
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volatile uint8_t ACTV;
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uint8_t RSVDB[0x3f0 - 0x331];
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volatile uint8_t CFG_SEL;
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};
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#endif /* #ifndef _MEC_MCHP_UART_H */
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