77 lines
2.0 KiB
C
77 lines
2.0 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_PWM_H
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#define _MEC_PWM_H
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#include <stdint.h>
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#include <stddef.h>
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#define MCHP_PWM_INST_SPACING 0x10u
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#define MCHP_PWM_INST_SPACING_P2 4u
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/* PWM Count On register */
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#define MCHP_PWM_COUNT_ON_REG_OFS 0u
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#define MCHP_PWM_COUNT_ON_MASK 0xffffu
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/* PWM Count Off register */
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#define MCHP_PWM_COUNT_OFF_REG_OFS 4u
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#define MCHP_PWM_COUNT_OFF_MASK 0xffffu
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/* PWM Configuration Register */
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#define MCHP_PWM_CONFIG_REG_OFS 8u
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#define MCHP_PWM_CONFIG_MASK 0x7fu
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/*
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* Enable and start PWM. Clearing this bit resets internal counters.
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* COUNT_ON and COUNT_OFF registers are not affected by enable bit.
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*/
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#define MCHP_PWM_CFG_ENABLE_POS 0
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#define MCHP_PWM_CFG_ENABLE BIT(MCHP_PWM_CFG_ENABLE_POS)
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/* Clock select */
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#define MCHP_PWM_CFG_CLK_SEL_POS 1u
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#define MCHP_PWM_CFG_CLK_SEL_48M 0u
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#define MCHP_PWM_CFG_CLK_SEL_100K BIT(MCHP_PWM_CFG_CLK_SEL_POS)
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/*
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* ON state polarity.
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* Default ON state is High.
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*/
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#define MCHP_PWM_CFG_ON_POL_POS 2u
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#define MCHP_PWM_CFG_ON_POL_HI 0u
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#define MCHP_PWM_CFG_ON_POL_LO BIT(MCHP_PWM_CFG_ON_POL_POS)
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/*
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* Clock pre-divider
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* Clock divider value = pre-divider + 1
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*/
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#define MCHP_PWM_CFG_CLK_PRE_DIV_POS 3u
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#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK0 0x0fU
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#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK \
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SHLU32(0x0fu, MCHP_PWM_CFG_CLK_PRE_DIV_POS)
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#define MCHP_PWM_CFG_CLK_PRE_DIV(n) \
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SHLU32((n) & MCHP_PWM_CFG_CLK_PRE_DIV_MASK0, \
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MCHP_PWM_CFG_CLK_PRE_DIV_POS)
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/* PWM input frequencies selected in configuration register. */
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#define MCHP_PWM_INPUT_FREQ_HI 48000000u
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#define MCHP_PWM_INPUT_FREQ_LO 100000u
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/*
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* PWM Frequency =
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* (1 / (pre_div + 1)) * PWM_INPUT_FREQ / ((COUNT_ON+1) + (COUNT_OFF+1))
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*
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* PWM Duty Cycle =
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* (COUNT_ON+1) / ((COUNT_ON+1) + (COUNT_OFF + 1))
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*/
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/** @brief PWM controller */
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struct pwm_regs {
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volatile uint32_t COUNT_ON;
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volatile uint32_t COUNT_OFF;
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volatile uint32_t CONFIG;
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};
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#endif /* #ifndef _MEC_PWM_H */
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