154 lines
4.9 KiB
C
154 lines
4.9 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_PECI_H
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#define _MEC_PECI_H
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#include <stdint.h>
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#include <stddef.h>
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/* Write Data register */
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#define MCHP_PECI_WR_DATA_REG_OFS 0u
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#define MCHP_PECI_WR_DATA_MASK 0xffu
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/* Read Data register */
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#define MCHP_PECI_RD_DATA_REG_OFS 4u
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#define MCHP_PECI_RD_DATA_MASK 0xffu
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/* Control register */
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#define MCHP_PECI_CTRL_REG_OFS 8u
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#define MCHP_PECI_CTRL_MASK 0xe9u
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#define MCHP_PECI_CTRL_PD_POS 0
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#define MCHP_PECI_CTRL_PD BIT(MCHP_PECI_CTRL_PD_POS)
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#define MCHP_PECI_CTRL_RST_POS 3
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#define MCHP_PECI_CTRL_RST BIT(MCHP_PECI_CTRL_RST_POS)
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#define MCHP_PECI_CTRL_FRST_POS 5
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#define MCHP_PECI_CTRL_FRST BIT(MCHP_PECI_CTRL_FRST_POS)
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#define MCHP_PECI_CTRL_TXEN_POS 6
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#define MCHP_PECI_CTRL_TXEN BIT(MCHP_PECI_CTRL_TXEN_POS)
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#define MCHP_PECI_CTRL_MIEN_POS 7
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#define MCHP_PECI_CTRL_MIEN BIT(MCHP_PECI_CTRL_MIEN_POS)
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/* Status 1 register. RW1C and read-only bits. */
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#define MCHP_PECI_STS1_REG_OFS 0x0cu
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#define MCHP_PECI_STS1_MASK 0xbfu
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#define MCHP_PECI_STS1_BOF_POS 0
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#define MCHP_PECI_STS1_BOF BIT(MCHP_PECI_STS1_BOF_POS)
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#define MCHP_PECI_STS1_EOF_POS 1
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#define MCHP_PECI_STS1_EOF BIT(MCHP_PECI_STS1_EOF_POS)
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/* Error is read-only */
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#define MCHP_PECI_STS1_ERR_POS 2
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#define MCHP_PECI_STS1_ERR BIT(MCHP_PECI_STS1_ERR_POS)
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/* Ready is read-only */
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#define MCHP_PECI_STS1_RDY_POS 3
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#define MCHP_PECI_STS1_RDY BIT(MCHP_PECI_STS1_RDY_POS)
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#define MCHP_PECI_STS1_RDYLO_POS 4
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#define MCHP_PECI_STS1_RDYLO BIT(MCHP_PECI_STS1_RDYLO_POS)
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#define MCHP_PECI_STS1_RDYHI_POS 5
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#define MCHP_PECI_STS1_RDYHI BIT(MCHP_PECI_STS1_RDYHI_POS)
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/* MINT is read-only */
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#define MCHP_PECI_STS1_MINT_POS 7
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#define MCHP_PECI_STS1_MINT BIT(MCHP_PECI_STS1_MINT_POS)
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/* Status 2 register. Read-only bits. */
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#define MCHP_PECI_STS2_REG_OFS 0x10u
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#define MCHP_PECI_STS2_MASK 0x8fu
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#define MCHP_PECI_STS2_WFF_POS 0
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#define MCHP_PECI_STS2_WFF BIT(MCHP_PECI_STS2_WFF_POS)
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#define MCHP_PECI_STS2_WFE_POS 1
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#define MCHP_PECI_STS2_WFE BIT(MCHP_PECI_STS2_WFE_POS)
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#define MCHP_PECI_STS2_RFF_POS 2
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#define MCHP_PECI_STS2_RFF BIT(MCHP_PECI_STS2_RFF_POS)
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#define MCHP_PECI_STS2_RFE_POS 3
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#define MCHP_PECI_STS2_RFE BIT(MCHP_PECI_STS2_RFE_POS)
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#define MCHP_PECI_STS2_IDLE_POS 7
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#define MCHP_PECI_STS2_IDLE BIT(MCHP_PECI_STS2_IDLE_POS)
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/* Error register. R/W1C bits. */
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#define MCHP_PECI_ERR_REG_OFS 0x14u
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#define MCHP_PECI_ERR_MASK 0xf3u
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#define MCHP_PECI_ERR_FERR_POS 0
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#define MCHP_PECI_ERR_FERR BIT(MCHP_PECI_ERR_FERR_POS)
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#define MCHP_PECI_ERR_BERR_POS 1
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#define MCHP_PECI_ERR_BERR BIT(MCHP_PECI_ERR_BERR_POS)
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#define MCHP_PECI_ERR_WROV_POS 4
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#define MCHP_PECI_ERR_WROV BIT(MCHP_PECI_ERR_WROV_POS)
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#define MCHP_PECI_ERR_WRUN_POS 5
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#define MCHP_PECI_ERR_WRUN BIT(MCHP_PECI_ERR_WRUN_POS)
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#define MCHP_PECI_ERR_RDOV_POS 6
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#define MCHP_PECI_ERR_RDOV BIT(MCHP_PECI_ERR_RDOV_POS)
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#define MCHP_PECI_ERR_CLK_POS 7
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#define MCHP_PECI_ERR_CLK BIT(MCHP_PECI_ERR_CLK_POS)
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/* Interrupt Enable 1 register. */
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#define MCHP_PECI_IEN1_REG_OFS 0x18u
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#define MCHP_PECI_IEN1_MASK 0x37u
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#define MCHP_PECI_IEN1_BIEN_POS 0
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#define MCHP_PECI_IEN1_BIEN BIT(MCHP_PECI_IEN1_BIEN_POS)
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#define MCHP_PECI_IEN1_EIEN_POS 1
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#define MCHP_PECI_IEN1_EIEN BIT(MCHP_PECI_IEN1_EIEN_POS)
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#define MCHP_PECI_IEN1_EREN_POS 2
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#define MCHP_PECI_IEN1_EREN BIT(MCHP_PECI_IEN1_EREN_POS)
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#define MCHP_PECI_IEN1_RLEN_POS 4
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#define MCHP_PECI_IEN1_RLEN BIT(MCHP_PECI_IEN1_RLEN_POS)
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#define MCHP_PECI_IEN1_RHEN_POS 5
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#define MCHP_PECI_IEN1_RHEN BIT(MCHP_PECI_IEN1_RHEN_POS)
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/* Interrupt Enable 2 register. */
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#define MCHP_PECI_IEN2_REG_OFS 0x1cu
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#define MCHP_PECI_IEN2_MASK 0x06u
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#define MCHP_PECI_IEN2_ENWFE_POS 1
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#define MCHP_PECI_IEN2_ENWFE BIT(MCHP_PECI_IEN2_ENWFE_POS)
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#define MCHP_PECI_IEN2_ENRFF_POS 2
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#define MCHP_PECI_IEN2_ENRFF BIT(MCHP_PECI_IEN2_ENRFF_POS)
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/* Optimal Bit Time LSB register. */
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#define MCHP_PECI_OPT_BT_LSB_REG_OFS 0x20u
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#define MCHP_PECI_OPT_BT_LSB_MASK 0xffu
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/* Optimal Bit Time MSB register. */
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#define MCHP_PECI_OPT_BT_MSB_REG_OFS 0x24u
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#define MCHP_PECI_OPT_BT_MSB_MASK 0xffu
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/** @brief PECI controller. Size = 76(0x4c) */
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struct peci_regs {
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volatile uint8_t WR_DATA;
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uint8_t RSVD1[3];
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volatile uint8_t RD_DATA;
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uint8_t RSVD2[3];
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volatile uint8_t CONTROL;
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uint8_t RSVD3[3];
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volatile uint8_t STATUS1;
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uint8_t RSVD4[3];
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volatile uint8_t STATUS2;
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uint8_t RSVD5[3];
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volatile uint8_t ERROR;
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uint8_t RSVD6[3];
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volatile uint8_t INT_EN1;
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uint8_t RSVD7[3];
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volatile uint8_t INT_EN2;
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uint8_t RSVD8[3];
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volatile uint8_t OPT_BIT_TIME_LSB;
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uint8_t RSVD9[3];
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volatile uint8_t OPT_BIT_TIME_MSB;
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uint8_t RSVD10[3];
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volatile uint8_t REQ_TMR_LSB;
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uint8_t RSVD11[3];
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volatile uint8_t REQ_TMR_MSB;
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uint8_t RSVD12[3];
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volatile uint8_t BAUD_CTRL;
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uint8_t RSVD13[3];
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uint32_t RSVD14[3];
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volatile uint8_t BLK_ID;
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uint8_t RSVD15[3];
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volatile uint8_t BLK_REV;
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uint8_t RSVD16[3];
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volatile uint8_t SST_CTL1;
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uint8_t RSVD17[3];
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};
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#endif /* #ifndef _MEC_PECI_H */
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