120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_KBC_H
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#define _MEC_KBC_H
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#include <stdint.h>
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#include <stddef.h>
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/* ---- EM8042 Keyboard Controller (KBC) ---- */
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/* EC_KBC_STS and KBC_STS_RD bit definitions */
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#define MCHP_KBC_STS_OBF_POS 0u
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#define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
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#define MCHP_KBC_STS_IBF_POS 1u
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#define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS)
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#define MCHP_KBC_STS_UD0_POS 2u
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#define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS)
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#define MCHP_KBC_STS_CD_POS 3u
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#define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS)
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#define MCHP_KBC_STS_UD1_POS 4u
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#define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS)
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#define MCHP_KBC_STS_AUXOBF_POS 5u
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#define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS)
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#define MCHP_KBC_STS_UD2_POS 6u
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#define MCHP_KBC_STS_UD2_MASK0 0x03u
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#define MCHP_KBC_STS_UD2_MASK 0xc0u
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#define MCHP_KBC_STS_UD2_0_POS 6u
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#define MCHP_KBC_STS_UD2_0 BIT(6)
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#define MCHP_KBC_STS_UD2_1 BIT(7)
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/* KBC_CTRL bit definitions */
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#define MCHP_KBC_CTRL_UD3_POS 0u
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#define MCHP_KBC_CTRL_UD3 BIT(MCHP_KBC_CTRL_UD3_POS)
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#define MCHP_KBC_CTRL_SAEN_POS 1u
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#define MCHP_KBC_CTRL_SAEN BIT(MCHP_KBC_CTRL_SAEN_POS)
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#define MCHP_KBC_CTRL_PCOBFEN_POS 2u
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#define MCHP_KBC_CTRL_PCOBFEN BIT(MCHP_KBC_CTRL_PCOBFEN_POS)
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#define MCHP_KBC_CTRL_UD4_POS 3u
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#define MCHP_KBC_CTRL_UD4_MASK0 0x03u
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#define MCHP_KBC_CTRL_UD4_MASK 0x18u
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#define MCHP_KBC_CTRL_OBFEN_POS 5u
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#define MCHP_KBC_CTRL_OBFEN BIT(MCHP_KBC_CTRL_OBFEN_POS)
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#define MCHP_KBC_CTRL_UD5_POS 6u
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#define MCHP_KBC_CTRL_UD5 BIT(MCHP_KBC_CTRL_UD5_POS)
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#define MCHP_KBC_CTRL_AUXH_POS 7u
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#define MCHP_KBC_CTRL_AUXH BIT(MCHP_KBC_CTRL_AUXH_POS)
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/* PCOBF register bit definitions */
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#define MCHP_KBC_PCOBF_EN_POS 0u
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#define MCHP_KBC_PCOBF_EN BIT(MCHP_KBC_PCOBF_EN_POS)
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/* KBC_PORT92_EN register bit definitions */
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#define MCHP_KBC_PORT92_EN_POS 0u
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#define MCHP_KBC_PORT92_EN BIT(MCHP_KBC_PORT92_EN_POS)
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/* HOST Port 92h emulation registers */
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#define MCHP_PORT92_HOST_MASK GENMASK(1, 0)
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#define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0
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#define MCHP_PORT92_HOST_ALT_CPU_RST BIT(0)
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#define MCHP_PORT92_HOST_ALT_GA20_POS 1
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#define MCHP_PORT92_HOST_ALT_GA20 BIT(1)
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/* GATEA20_CTRL */
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#define MCHP_PORT92_GA20_CTRL_MASK BIT(0)
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#define MCHP_PORT92_GA20_CTRL_VAL_POS 0
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#define MCHP_PORT92_GA20_CTRL_VAL_HI BIT(0)
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/*
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* SETGA20L - writes of any data to this register causes
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* GATEA20 latch to be set.
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*/
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#define MCHP_PORT92_SETGA20L_MASK BIT(0)
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#define MCHP_PORT92_SETGA20L_SET_POS 0
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#define MCHP_PORT92_SETGA20L_SET BIT(0)
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/*
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* RSTGA20L - writes of any data to this register causes
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* the GATEA20 latch to be reset
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*/
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#define MCHP_PORT92_RSTGA20L_MASK BIT(0)
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#define MCHP_PORT92_RSTGA20L_SET_POS 0
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#define MCHP_PORT92_RSTGA20L_RST BIT(0)
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/* ACTV */
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#define MCHP_PORT92_ACTV_MASK BIT(0)
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#define MCHP_PORT92_ACTV_ENABLE BIT(0)
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/** @brief 8042 Emulated Keyboard controller. Size = 820(0x334) */
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struct kbc_regs {
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volatile uint32_t HOST_AUX_DATA;
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volatile uint32_t KBC_STS_RD;
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uint8_t RSVD1[0x100 - 0x08];
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volatile uint32_t EC_DATA;
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volatile uint32_t EC_KBC_STS;
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volatile uint32_t KBC_CTRL;
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volatile uint32_t EC_AUX_DATA;
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uint32_t RSVD2[1];
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volatile uint32_t PCOBF;
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uint8_t RSVD3[0x0330 - 0x0118];
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volatile uint32_t KBC_PORT92_EN;
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};
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/** @brief Fast Port92h Registers (PORT92) */
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struct port92_regs {
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volatile uint32_t HOST_P92;
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uint8_t RSVD1[0x100u - 0x04u];
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volatile uint32_t GATEA20_CTRL;
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uint32_t RSVD2[1];
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volatile uint32_t SETGA20L;
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volatile uint32_t RSTGA20L;
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uint8_t RSVD3[0x0330ul - 0x0110ul];
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volatile uint32_t ACTV;
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};
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#endif /* #ifndef _MEC_KBC_H */
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