61 lines
1.0 KiB
Plaintext
61 lines
1.0 KiB
Plaintext
/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#ifndef DT_DRAM_BASE
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#define DT_DRAM_BASE 0
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#endif
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#ifndef DT_DRAM_SIZE
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#define DT_DRAM_SIZE DT_SIZE_K(4096)
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#endif
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#include <intel/lakemont.dtsi>
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/ {
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model = "QEMU X86 (Lakemont) emulator";
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compatible = "qemu,x86_lakemont_emulator";
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aliases {
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uart-0 = &uart0;
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};
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chosen {
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zephyr,sram = &dram0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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dram0: memory@0 {
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device_type = "memory";
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reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
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};
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soc {
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "okay";
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};
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hpet: hpet@fed00000 {
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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};
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};
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