93 lines
3.1 KiB
C
93 lines
3.1 KiB
C
/*
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* Copyright (c) 2017, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qm_ss_interrupt.h"
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#include "qm_soc_regs.h"
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#include "qm_sensor_regs.h"
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/* SCSS base addr for Sensor Subsystem interrupt routing, for linear IRQ
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* mapping */
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#define INTERRUPT_ROUTER_SS_INT_MASK_BASE \
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(&QM_INTERRUPT_ROUTER->ss_adc_0_error_int_mask)
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#if (UNIT_TEST)
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qm_ss_isr_t __ivt_vect_table[QM_SS_INT_VECTOR_NUM];
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#else
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extern qm_ss_isr_t __ivt_vect_table[];
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#endif
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void qm_ss_irq_disable(void)
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{
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__builtin_arc_clri();
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}
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void qm_ss_irq_enable(void)
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{
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__builtin_arc_seti(0);
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}
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void qm_ss_irq_mask(uint32_t irq)
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{
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__builtin_arc_sr(irq, QM_SS_AUX_IRQ_SELECT);
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__builtin_arc_sr(QM_SS_INT_DISABLE, QM_SS_AUX_IRQ_ENABLE);
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}
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void qm_ss_irq_unmask(uint32_t irq)
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{
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__builtin_arc_sr(irq, QM_SS_AUX_IRQ_SELECT);
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__builtin_arc_sr(QM_SS_INT_ENABLE, QM_SS_AUX_IRQ_ENABLE);
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}
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void qm_ss_int_vector_request(uint32_t vector, qm_ss_isr_t isr)
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{
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/* Invalidate the I-cache line which contains the irq vector. This
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* will bypass I-Cach and set vector with the good isr. */
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__builtin_arc_sr((uint32_t)&__ivt_vect_table[0] + (vector * 4),
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QM_SS_AUX_IC_IVIL);
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/* All SR accesses to the IC_IVIL register must be followed by three
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* NOP instructions, see chapter 3.3.59 in the datasheet
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* "ARC_V2_ProgrammersReference.pdf" */
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__builtin_arc_nop();
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__builtin_arc_nop();
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__builtin_arc_nop();
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__ivt_vect_table[vector] = isr;
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}
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void qm_ss_irq_request(uint32_t irq, qm_ss_isr_t isr)
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{
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uint32_t vector = irq + (QM_SS_EXCEPTION_NUM + QM_SS_INT_TIMER_NUM);
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/* Guarding the IRQ set-up */
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qm_ss_irq_mask(vector);
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qm_ss_int_vector_request(vector, isr);
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qm_ss_irq_unmask(vector);
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}
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