223 lines
5.0 KiB
ArmAsm
223 lines
5.0 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Handling of transitions to-and-from regular IRQs (RIRQ)
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*
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* This module implements the code for handling entry to and exit from regular
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* IRQs.
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*
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* See isr_wrapper.S for details.
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*/
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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GTEXT(_rirq_enter)
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GTEXT(_rirq_exit)
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GTEXT(_rirq_common_interrupt_swap)
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GDATA(exc_nest_count)
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#if 0 /* TODO: when FIRQ is not present, all would be regular */
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#define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
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#else
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#define NUM_REGULAR_IRQ_PRIO_LEVELS (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
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#endif
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/* note: the above define assumes that prio 0 IRQ is for FIRQ, and
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* that all others are regular interrupts.
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* TODO: Revist this if FIRQ becomes configurable.
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*/
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/**
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*
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* @brief Work to be done before handing control to an IRQ ISR
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*
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* The processor pushes automatically all registers that need to be saved.
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* However, since the processor always runs at kernel privilege there is no
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* automatic switch to the IRQ stack: this must be done in software.
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*
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* Assumption by _isr_demux: r3 is untouched by _rirq_enter.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_enter)
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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#endif
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clri
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ld r1, [exc_nest_count]
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add r0, r1, 1
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st r0, [exc_nest_count]
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cmp r1, 0
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bgt.d rirq_nest
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mov r0, sp
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mov r1, _kernel
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ld sp, [r1, _kernel_offset_to_irq_stack]
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rirq_nest:
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push_s r0
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seti
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j _isr_demux
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/**
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*
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* @brief Work to be done exiting an IRQ
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_exit)
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clri
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pop sp
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mov r1, exc_nest_count
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ld r0, [r1]
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sub r0, r0, 1
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cmp r0, 0
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bne.d _rirq_return_from_rirq
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st r0, [r1]
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#ifdef CONFIG_STACK_SENTINEL
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bl _check_stack_sentinel
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#endif
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#ifdef CONFIG_PREEMPT_ENABLED
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mov r1, _kernel
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ld_s r2, [r1, _kernel_offset_to_current]
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/*
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* Lock interrupts to ensure kernel queues do not change from this
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* point on until return from interrupt.
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*/
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/*
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* Both (a)reschedule and (b)non-reschedule cases need to load the
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* current thread's stack, but don't have to use it until the decision
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* is taken: load the delay slots with the 'load stack pointer'
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* instruction.
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*
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* a) needs to load it to save outgoing context.
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* b) needs to load it to restore the interrupted context.
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*/
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/* check if the current thread needs to be rescheduled */
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ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
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cmp_s r0, r2
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beq _rirq_no_reschedule
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/* cached thread to run is in r0, fall through */
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.balign 4
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_rirq_reschedule:
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/* _save_callee_saved_regs expects outgoing thread in r2 */
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_save_callee_saved_regs
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st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
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/* incoming thread is in r0: it becomes the new 'current' */
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mov r2, r0
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st_s r2, [r1, _kernel_offset_to_current]
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.balign 4
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_rirq_common_interrupt_swap:
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/* r2 contains pointer to new thread */
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* Use stack top and base registers from restored context */
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ld r3, [r2, _thread_offset_to_stack_base]
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sr r3, [_ARC_V2_KSTACK_BASE]
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ld r3, [r2, _thread_offset_to_stack_top]
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sr r3, [_ARC_V2_KSTACK_TOP]
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#endif
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/*
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* _load_callee_saved_regs expects incoming thread in r2.
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* _load_callee_saved_regs restores the stack pointer.
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*/
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_load_callee_saved_regs
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#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
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push_s r2
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mov r0, r2
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bl configure_mpu_thread
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pop_s r2
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#endif
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ld_s r3, [r2, _thread_offset_to_relinquish_cause]
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breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
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nop
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breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
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nop
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/* fall through */
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.balign 4
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_rirq_return_from_coop:
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/*
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* status32, sec_stat (when CONFIG_ARC_HAS_SECURE is enabled) and pc
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* (blink) are already on the stack in the right order
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*/
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ld_s r0, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
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/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
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ld_s r3, [r2, _thread_offset_to_intlock_key]
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st 0, [r2, _thread_offset_to_intlock_key]
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cmp r3, 0
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or.ne r0, r0, _ARC_V2_STATUS32_IE
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st_s r0, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
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/* carve fake stack */
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sub sp, sp, ___isf_t_pc_OFFSET
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/* update return value on stack */
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ld_s r0, [r2, _thread_offset_to_return_value]
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st_s r0, [sp, ___isf_t_r0_OFFSET]
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/*
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* r13 is part of both the callee and caller-saved register sets because
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* the processor is only able to save registers in pair in the regular
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* IRQ prologue. r13 thus has to be set to its correct value in the IRQ
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* stack frame.
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*/
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st_s r13, [sp, ___isf_t_r13_OFFSET]
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/* stack now has the IRQ stack frame layout, pointing to r0 */
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/* fall through to rtie instruction */
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/* rtie will pop the rest from the stack */
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/* fall through to rtie instruction */
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#endif /* CONFIG_PREEMPT_ENABLED */
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.balign 4
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_rirq_return_from_firq:
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_rirq_return_from_rirq:
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_rirq_no_reschedule:
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rtie
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