dcc5dd27fa
This commit makes the RV32M1 SoC rely on the default behavior of relying on the `CONFIG_RISCV_ISA_EXT_*` config options, and removes the `zephyr_compile_options` override when the standard toolchain is used. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> |
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rv32m1 |