46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Code to compensate for Lakemont EOI forwarding bug
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*
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* Lakemont CPU on Quark SE has a bug where LOAPIC EOI does not
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* correctly forward EOI to the IOAPIC, causing the IRR bit in the RTE
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* to never get cleared. We need to set the IOAPIC EOI register manually
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* with the vector of the interrupt.
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*/
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#include <nanokernel.h>
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#include <arch/x86/irq_controller.h>
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#include <sys_io.h>
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#include <interrupt_controller/ioapic_priv.h>
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void _lakemont_eoi(void)
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{
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/* It is difficult to know whether the IRQ being serviced is
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* a level interrupt handled by the IOAPIC; the only information
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* we have is the vector # in the IDT. So unconditionally
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* write to IOAPIC_EOI for every interrupt
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*/
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sys_write32(_irq_controller_isr_vector_get(),
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CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_EOI);
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/* Send EOI to the LOAPIC as well */
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sys_write32(0, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI);
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}
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