164 lines
4.2 KiB
C
164 lines
4.2 KiB
C
/* Copyright 2023 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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/* Be warned: the interface here is poorly understood. I did the best
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* I could to transcribe it (with a little clarification and
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* optimization) from the SOF mt8195 source, but without docs this
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* needs to be treated with great care.
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*
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* Notes:
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* * power-on default is 26Mhz, confirmed with a hacked SOF that
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* loads but stubs out the clk code.
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* * The original driver has a 13Mhz mode too, but it doesn't work (it
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* hits all the same code and data paths as 26MHz and acts as a
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* duplicate.
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* * The magic numbers in the pll_con2 field are from the original
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* source. No docs on the PLL register interface are provided.
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*/
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struct mtk_pll_control {
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uint32_t con0;
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uint32_t con1;
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uint32_t con2;
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uint32_t con3;
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uint32_t con4;
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};
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#define MTK_PLL_CTRL (*(volatile struct mtk_pll_control *) \
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DT_PROP(DT_NODELABEL(cpuclk), pll_ctrl_reg))
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#define MTK_PLL_CON0_BASE_EN BIT(0)
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#define MTK_PLL_CON0_EN BIT(9)
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#define MTK_PLL_CON4_ISO_EN BIT(1)
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#define MTK_PLL_CON4_PWR_ON BIT(0)
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struct mtk_clk_gen {
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uint32_t mode;
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uint32_t update[4];
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uint32_t _unused[3];
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struct {
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uint32_t cur;
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uint32_t set;
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uint32_t clr;
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} clk_cfg[29];
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};
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#define MTK_CLK_GEN (*(volatile struct mtk_clk_gen *) \
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DT_REG_ADDR(DT_NODELABEL(cpuclk)))
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#define MTK_CLK22_SEL_PLL 8
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#define MTK_CLK22_SEL_26M 0
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#define MTK_CLK28_SEL_PLL 7
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#define MTK_CLK28_SEL_26M 0
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#define MTK_CK_CG (*(volatile uint32_t *) \
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DT_PROP(DT_NODELABEL(cpuclk), cg_reg))
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#define MTK_CK_CG_SW 1
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const struct { uint16_t mhz; bool pll; uint32_t pll_con2; } freqs[] = {
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{ 26, false, 0 },
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{ 370, true, 0x831c7628 },
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{ 540, true, 0x8214c4ed },
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{ 720, true, 0x821bb13c },
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};
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static int cur_idx;
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/* Can't use CPU-counted loops when changing CPU speed, and don't have
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* an OS timer driver yet. Use the 13 MHz timer hardware directly.
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* (The ostimer is always running AFAICT, there's not even an
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* interface for a disable bit defined)
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*/
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#define TIMER (((volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(ostimer64)))[3])
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static inline void delay_us(int us)
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{
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uint32_t t0 = TIMER;
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while (TIMER - t0 < (us * 13)) {
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}
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}
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static void set_pll_power(bool on)
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{
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if (on) {
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MTK_CK_CG &= ~MTK_CK_CG_SW;
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MTK_PLL_CTRL.con4 |= MTK_PLL_CON4_PWR_ON;
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delay_us(1);
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MTK_PLL_CTRL.con4 &= ~MTK_PLL_CON4_ISO_EN;
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delay_us(1);
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MTK_PLL_CTRL.con0 |= MTK_PLL_CON0_EN;
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delay_us(20);
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} else {
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MTK_PLL_CTRL.con0 &= ~MTK_PLL_CON0_EN;
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delay_us(1);
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MTK_PLL_CTRL.con4 |= MTK_PLL_CON4_ISO_EN;
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delay_us(1);
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MTK_PLL_CTRL.con4 &= ~MTK_PLL_CON4_PWR_ON;
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}
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}
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/* Oddball utility. There is a giant array of clocks (of which SOF
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* only touches two), each with "clear" and "set" registers which are
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* used to set 4-bit fields at a specific offset. After that, a
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* particular bit in one of the "update" registers must be written,
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* presumably to latch the input.
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*/
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static void setclk(int clk, int shift, int updreg, int ubit, int val)
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{
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MTK_CLK_GEN.clk_cfg[clk].clr = (0xf << shift);
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if (val) {
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MTK_CLK_GEN.clk_cfg[clk].set = (val << shift);
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}
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MTK_CLK_GEN.update[updreg] = BIT(ubit);
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}
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#define SETCLK22(val) setclk(22, 0, 2, 24, (val))
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#define SETCLK28(val) setclk(28, 16, 3, 18, (val))
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void mtk_adsp_set_cpu_freq(int mhz)
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{
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int idx;
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for (idx = 0; idx < ARRAY_SIZE(freqs); idx++) {
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if (freqs[idx].mhz == mhz) {
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break;
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}
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}
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if (idx == cur_idx || freqs[idx].mhz != mhz) {
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return;
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}
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if (freqs[idx].pll) {
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/* Switch to PLL from 26Mhz */
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set_pll_power(true);
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SETCLK22(MTK_CLK22_SEL_PLL);
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SETCLK28(MTK_CLK28_SEL_PLL);
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MTK_PLL_CTRL.con2 = freqs[idx].pll_con2;
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} else {
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/* Switch to 26Mhz from PLL */
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SETCLK28(MTK_CLK28_SEL_26M);
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SETCLK22(MTK_CLK22_SEL_26M);
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set_pll_power(false);
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}
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cur_idx = idx;
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}
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/* The CPU clock is not affected (!) by device reset, so we don't know
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* the speed we're at (on MT8195, hardware powers up at 26 Mhz, but
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* production SOF firmware sets it to 720 at load time and leaves it
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* there). Set the lowest, then the highest speed unconditionally to
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* force the transition.
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*/
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void mtk_adsp_cpu_freq_init(void)
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{
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mtk_adsp_set_cpu_freq(freqs[0].mhz);
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mtk_adsp_set_cpu_freq(freqs[ARRAY_SIZE(freqs) - 1].mhz);
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}
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