zephyr/dts/arm
David Leach a09ba37334 MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-18 14:29:53 +01:00
..
acsip
atmel drivers: serial: uart_sam0: Fix sercom5 pinctrl pad per datasheet 2021-09-21 12:51:56 -04:00
broadcom
cypress dts: psoc6: Use valid IRQ prio levels for CM4 2021-08-11 10:06:13 -05:00
gigadevice drivers: serial: Add gd32 uart driver 2021-10-28 11:17:25 +02:00
infineon
microchip Microchip: MEC172x: eSPI driver 2021-10-26 09:27:20 -04:00
nordic drivers: audio: dmic: Add support for nRF PDM peripherals 2021-09-03 09:34:06 -04:00
nuvoton drivers: spi: npcx: add SPI support to access the SPI flash 2021-11-01 21:48:20 -04:00
nxp MXRT600: Fix secure/non-secure definition for FLEXSPI 2021-11-18 14:29:53 +01:00
quicklogic
renesas/gen3
seeed dts/arm/seeed: lora-e5: Update hse clock configuration 2021-08-24 07:19:12 -04:00
silabs boards: efr32mg_sltb004a: Add minimal pwm support 2021-09-03 10:11:15 -04:00
st dts: arm: stm32: TIM6 and TIM7 doesn't support PWM capability 2021-11-16 09:55:30 -06:00
ti
xilinx soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data 2021-10-28 15:26:50 +02:00
armv6-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv7-a.dtsi soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data 2021-10-28 15:26:50 +02:00
armv7-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv7-r.dtsi
armv8-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv8.1-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00