zephyr/soc/xtensa
Anas Nashif f336a8ea1b soc: intel_adsp: set trace size to non-zero
Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-12 20:53:40 -05:00
..
esp32 esp32: workaround esptool linker sections limit 2020-10-13 08:53:39 -07:00
intel_adsp soc: intel_adsp: set trace size to non-zero 2021-01-12 20:53:40 -05:00
intel_s1000 xtensa: set toolchain variant per SoC 2020-12-20 14:30:50 -05:00
sample_controller xtensa: set toolchain variant per SoC 2020-12-20 14:30:50 -05:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00