154 lines
4.2 KiB
C
154 lines
4.2 KiB
C
/* spi_dw_quark_se_ss.h - Designware SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_DW_QUARK_SE_SS_H__
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#define __SPI_DW_QUARK_SE_SS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Registers:
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* Some registers have been collapsed into one
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* - SER is part of SSIENR
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* - TXFTLR is part of RXFTLR
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* This requires a little bit different access functions
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* see below: write_ser(), write_rxftlr() and write_txftlr()
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*/
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#define DW_SPI_REG_CTRLR0 (0x00)
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#define DW_SPI_REG_SSIENR (0x02)
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#define DW_SPI_REG_BAUDR (0x04)
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#define DW_SPI_REG_RXFTLR (0x05)
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#define DW_SPI_REG_TXFLR (0x07)
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#define DW_SPI_REG_RXFLR (0x08)
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#define DW_SPI_REG_SR (0x09)
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#define DW_SPI_REG_ISR (0x0a)
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#define DW_SPI_REG_IMR (0x0b)
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#define DW_SPI_REG_ICR (0x0c)
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#define DW_SPI_REG_DR (0x0d)
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#define DW_SPI_CTRLR0_CLK_ENA_BIT (15)
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#define DW_SPI_CTRLR0_CLK_ENA_MASK BIT(DW_SPI_CTRLR0_CLK_ENA_BIT)
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#define DW_SPI_QSS_SSIENR_SER(__slv) (__slv << 4)
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#define DW_SPI_QSS_TXFTLR(__lvl) (__lvl << 16)
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#define DW_SPI_QSS_SER_MASK (0xf0)
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#define DW_SPI_QSS_RXFTLR_MASK (0x0000ffff)
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#define DW_SPI_QSS_TXFTLR_MASK (0xffff0000)
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#define DW_SPI_DR_WD_BIT (30)
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#define DW_SPI_DR_WD_MASK BIT(DW_SPI_DR_WD_BIT)
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#define DW_SPI_DR_STROBE_BIT (31)
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#define DW_SPI_DR_STROBE_MASK BIT(DW_SPI_DR_STROBE_BIT)
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#define DW_SPI_DR_WRITE (DW_SPI_DR_STROBE_MASK | \
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DW_SPI_DR_WD_MASK)
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#define DW_SPI_DR_READ (DW_SPI_DR_STROBE_MASK)
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/* Register helpers
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* *_b functions only used for creating proper ser one
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*/
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/* CTRLR0 on Quark SE SS has a CLK_ENA bit we want to keep
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* as it is while writing the configuration.
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* *_b function only used for creating proper ser one
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*/
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DEFINE_MM_REG_READ(ctrlr0_b, DW_SPI_REG_CTRLR0, 16)
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static inline u32_t read_ctrlr0(u32_t addr)
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{
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return read_ctrlr0_b(addr);
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}
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DEFINE_MM_REG_WRITE(ctrlr0_b, DW_SPI_REG_CTRLR0, 16)
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static inline void write_ctrlr0(u32_t data, u32_t addr)
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{
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write_ctrlr0_b((read_ctrlr0_b(addr) & DW_SPI_CTRLR0_CLK_ENA_MASK) |
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data, addr);
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}
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DEFINE_MM_REG_READ(ctrlr1_b, DW_SPI_REG_CTRLR0, 32)
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DEFINE_MM_REG_WRITE(ctrlr1_b, DW_SPI_REG_CTRLR0, 32)
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static inline void write_ctrlr1(u32_t data, u32_t addr)
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{
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write_ctrlr1_b((read_ctrlr1_b(addr) & (data << 16)), addr);
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}
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DEFINE_MM_REG_READ(ssienr_b, DW_SPI_REG_SSIENR, 8)
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DEFINE_MM_REG_WRITE(ssienr_b, DW_SPI_REG_SSIENR, 8)
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static inline void write_ser(u32_t data, u32_t addr)
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{
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write_ssienr_b((read_ssienr_b(addr) & (~DW_SPI_QSS_SER_MASK)) |
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DW_SPI_QSS_SSIENR_SER(data), addr);
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}
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DEFINE_MM_REG_READ(rxftlr_b, DW_SPI_REG_RXFTLR, 32)
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DEFINE_MM_REG_WRITE(rxftlr_b, DW_SPI_REG_RXFTLR, 32)
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DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 16)
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static inline void write_rxftlr(u32_t data, u32_t addr)
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{
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write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_RXFTLR_MASK)) |
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data, addr);
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}
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static inline void write_txftlr(u32_t data, u32_t addr)
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{
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write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_TXFTLR_MASK)) |
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DW_SPI_QSS_TXFTLR(data), addr);
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}
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/* Quark SE SS requires to clear up all interrupts */
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DEFINE_MM_REG_WRITE(icr, DW_SPI_REG_ICR, 8)
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static inline void clear_interrupts(u32_t addr)
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{
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write_icr(0x1f, addr);
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}
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/* Reading and Writing Data
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* Quark SE SS DW SPI controller requires more logic from the driver which:
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* - needs to tell when it has been pushing in bits for TX FIFO
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* - needs to tell when it will be pulling out bits from RX FIFO
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*/
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DEFINE_MM_REG_WRITE(dr_b, DW_SPI_REG_DR, 32)
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DEFINE_MM_REG_READ(dr_b, DW_SPI_REG_DR, 32)
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static inline void write_dr(u32_t data, u32_t addr)
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{
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write_dr_b(data | DW_SPI_DR_WRITE, addr);
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}
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static inline u32_t read_dr(u32_t addr)
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{
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write_dr_b(DW_SPI_DR_READ, addr);
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__asm__("nop\n");
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return read_dr_b(addr);
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}
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/* Internal clock gating */
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DEFINE_SET_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
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DEFINE_CLEAR_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
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static inline void _extra_clock_on(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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set_bit_clk_ena(info->regs);
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}
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static inline void _extra_clock_off(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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clear_bit_clk_ena(info->regs);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SPI_DW_QUARK_SE_SS_H__ */
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