445 lines
10 KiB
C
445 lines
10 KiB
C
/*
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* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_MODULE_NAME eth_stm32_hal
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include <kernel.h>
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#include <device.h>
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#include <misc/__assert.h>
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#include <misc/util.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <net/net_pkt.h>
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#include <net/net_if.h>
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#include <net/ethernet.h>
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#include <ethernet/eth_stats.h>
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#include <soc.h>
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#include <misc/printk.h>
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#include <clock_control.h>
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#include <clock_control/stm32_clock_control.h>
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#include "eth_stm32_hal_priv.h"
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static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __aligned(4);
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static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __aligned(4);
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static u8_t dma_rx_buffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __aligned(4);
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static u8_t dma_tx_buffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __aligned(4);
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static inline void disable_mcast_filter(ETH_HandleTypeDef *heth)
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{
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__ASSERT_NO_MSG(heth != NULL);
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u32_t tmp = heth->Instance->MACFFR;
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/* disable multicast filtering */
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tmp &= ~(ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE |
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ETH_MULTICASTFRAMESFILTER_HASHTABLE |
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ETH_MULTICASTFRAMESFILTER_PERFECT);
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/* enable receiving all multicast frames */
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tmp |= ETH_MULTICASTFRAMESFILTER_NONE;
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heth->Instance->MACFFR = tmp;
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/* Wait until the write operation will be taken into account:
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* at least four TX_CLK/RX_CLK clock cycles
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*/
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tmp = heth->Instance->MACFFR;
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k_sleep(1);
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heth->Instance->MACFFR = tmp;
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}
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static int eth_tx(struct device *dev, struct net_pkt *pkt)
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{
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struct eth_stm32_hal_dev_data *dev_data = DEV_DATA(dev);
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ETH_HandleTypeDef *heth;
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u8_t *dma_buffer;
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int res;
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u16_t total_len;
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__IO ETH_DMADescTypeDef *dma_tx_desc;
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__ASSERT_NO_MSG(pkt != NULL);
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__ASSERT_NO_MSG(pkt->frags != NULL);
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__ASSERT_NO_MSG(dev != NULL);
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__ASSERT_NO_MSG(dev_data != NULL);
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heth = &dev_data->heth;
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k_mutex_lock(&dev_data->tx_mutex, K_FOREVER);
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total_len = net_pkt_get_len(pkt);
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if (total_len > ETH_TX_BUF_SIZE) {
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LOG_ERR("PKT to big");
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res = -EIO;
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goto error;
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}
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dma_tx_desc = heth->TxDesc;
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while ((dma_tx_desc->Status & ETH_DMATXDESC_OWN) != (u32_t)RESET) {
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k_yield();
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}
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dma_buffer = (u8_t *)(dma_tx_desc->Buffer1Addr);
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if (net_pkt_read_new(pkt, dma_buffer, total_len)) {
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res = -EIO;
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goto error;
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}
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if (HAL_ETH_TransmitFrame(heth, total_len) != HAL_OK) {
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LOG_ERR("HAL_ETH_TransmitFrame failed");
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res = -EIO;
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goto error;
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}
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/* When Transmit Underflow flag is set, clear it and issue a
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* Transmit Poll Demand to resume transmission.
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*/
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if ((heth->Instance->DMASR & ETH_DMASR_TUS) != (u32_t)RESET) {
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/* Clear TUS ETHERNET DMA flag */
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heth->Instance->DMASR = ETH_DMASR_TUS;
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/* Resume DMA transmission*/
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heth->Instance->DMATPDR = 0;
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res = -EIO;
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goto error;
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}
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res = 0;
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error:
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k_mutex_unlock(&dev_data->tx_mutex);
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return res;
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}
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static struct net_pkt *eth_rx(struct device *dev)
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{
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struct eth_stm32_hal_dev_data *dev_data;
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ETH_HandleTypeDef *heth;
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__IO ETH_DMADescTypeDef *dma_rx_desc;
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struct net_pkt *pkt;
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u16_t total_len;
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u8_t *dma_buffer;
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int i;
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__ASSERT_NO_MSG(dev != NULL);
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dev_data = DEV_DATA(dev);
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__ASSERT_NO_MSG(dev_data != NULL);
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heth = &dev_data->heth;
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if (HAL_ETH_GetReceivedFrame_IT(heth) != HAL_OK) {
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/* no frame available */
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return NULL;
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}
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total_len = heth->RxFrameInfos.length;
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dma_buffer = (u8_t *)heth->RxFrameInfos.buffer;
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pkt = net_pkt_rx_alloc_with_buffer(dev_data->iface, total_len,
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AF_UNSPEC, 0, K_NO_WAIT);
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if (!pkt) {
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LOG_ERR("Failed to obtain RX buffer");
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goto release_desc;
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}
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if (net_pkt_write_new(pkt, dma_buffer, total_len)) {
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LOG_ERR("Failed to append RX buffer to context buffer");
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net_pkt_unref(pkt);
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pkt = NULL;
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goto release_desc;
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}
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release_desc:
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/* Release descriptors to DMA */
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/* Point to first descriptor */
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dma_rx_desc = heth->RxFrameInfos.FSRxDesc;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i = 0; i < heth->RxFrameInfos.SegCount; i++) {
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dma_rx_desc->Status |= ETH_DMARXDESC_OWN;
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dma_rx_desc = (ETH_DMADescTypeDef *)
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(dma_rx_desc->Buffer2NextDescAddr);
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}
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/* Clear Segment_Count */
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heth->RxFrameInfos.SegCount = 0;
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/* When Rx Buffer unavailable flag is set: clear it
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* and resume reception.
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*/
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if ((heth->Instance->DMASR & ETH_DMASR_RBUS) != (u32_t)RESET) {
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/* Clear RBUS ETHERNET DMA flag */
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heth->Instance->DMASR = ETH_DMASR_RBUS;
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/* Resume DMA reception */
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heth->Instance->DMARPDR = 0;
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}
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if (!pkt) {
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eth_stats_update_errors_rx(dev_data->iface);
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}
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return pkt;
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}
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static void rx_thread(void *arg1, void *unused1, void *unused2)
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{
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struct device *dev;
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struct eth_stm32_hal_dev_data *dev_data;
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struct net_pkt *pkt;
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int res;
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__ASSERT_NO_MSG(arg1 != NULL);
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ARG_UNUSED(unused1);
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ARG_UNUSED(unused2);
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dev = (struct device *)arg1;
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dev_data = DEV_DATA(dev);
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__ASSERT_NO_MSG(dev_data != NULL);
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while (1) {
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k_sem_take(&dev_data->rx_int_sem, K_FOREVER);
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while ((pkt = eth_rx(dev)) != NULL) {
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net_pkt_print_frags(pkt);
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res = net_recv_data(dev_data->iface, pkt);
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if (res < 0) {
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eth_stats_update_errors_rx(dev_data->iface);
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LOG_ERR("Failed to enqueue frame "
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"into RX queue: %d", res);
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net_pkt_unref(pkt);
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}
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}
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}
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}
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static void eth_isr(void *arg)
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{
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struct device *dev;
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struct eth_stm32_hal_dev_data *dev_data;
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ETH_HandleTypeDef *heth;
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__ASSERT_NO_MSG(arg != NULL);
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dev = (struct device *)arg;
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dev_data = DEV_DATA(dev);
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__ASSERT_NO_MSG(dev_data != NULL);
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heth = &dev_data->heth;
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__ASSERT_NO_MSG(heth != NULL);
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HAL_ETH_IRQHandler(heth);
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}
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void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth_handle)
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{
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__ASSERT_NO_MSG(heth_handle != NULL);
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struct eth_stm32_hal_dev_data *dev_data =
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CONTAINER_OF(heth_handle, struct eth_stm32_hal_dev_data, heth);
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__ASSERT_NO_MSG(dev_data != NULL);
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k_sem_give(&dev_data->rx_int_sem);
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}
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static int eth_initialize(struct device *dev)
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{
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struct eth_stm32_hal_dev_data *dev_data;
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struct eth_stm32_hal_dev_cfg *cfg;
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int ret = 0;
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__ASSERT_NO_MSG(dev != NULL);
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dev_data = DEV_DATA(dev);
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cfg = DEV_CFG(dev);
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__ASSERT_NO_MSG(dev_data != NULL);
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__ASSERT_NO_MSG(cfg != NULL);
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dev_data->clock = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(dev_data->clock != NULL);
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/* enable clock */
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ret = clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken);
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ret |= clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken_tx);
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ret |= clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken_rx);
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ret |= clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken_ptp);
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if (ret) {
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LOG_ERR("Failed to enable ethernet clock");
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return -EIO;
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}
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__ASSERT_NO_MSG(cfg->config_func != NULL);
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cfg->config_func();
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return 0;
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}
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#if defined(CONFIG_ETH_STM32_HAL_RANDOM_MAC)
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static void generate_mac(u8_t *mac_addr)
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{
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u32_t entropy;
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entropy = sys_rand32_get();
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mac_addr[3] = entropy >> 8;
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mac_addr[4] = entropy >> 16;
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/* Locally administered, unicast */
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mac_addr[5] = ((entropy >> 0) & 0xfc) | 0x02;
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}
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#endif
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static void eth_iface_init(struct net_if *iface)
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{
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struct device *dev;
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struct eth_stm32_hal_dev_data *dev_data;
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ETH_HandleTypeDef *heth;
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u8_t hal_ret;
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__ASSERT_NO_MSG(iface != NULL);
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dev = net_if_get_device(iface);
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__ASSERT_NO_MSG(dev != NULL);
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dev_data = DEV_DATA(dev);
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__ASSERT_NO_MSG(dev_data != NULL);
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heth = &dev_data->heth;
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dev_data->iface = iface;
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#if defined(CONFIG_ETH_STM32_HAL_RANDOM_MAC)
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generate_mac(dev_data->mac_addr);
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#endif
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heth->Init.MACAddr = dev_data->mac_addr;
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hal_ret = HAL_ETH_Init(heth);
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if (hal_ret == HAL_TIMEOUT) {
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/* HAL Init time out. This could be linked to */
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/* a recoverable error. Log the issue and continue */
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/* driver initialisation */
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LOG_ERR("HAL_ETH_Init Timed out");
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} else if (hal_ret != HAL_OK) {
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LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
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return;
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}
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/* Initialize semaphores */
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k_mutex_init(&dev_data->tx_mutex);
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k_sem_init(&dev_data->rx_int_sem, 0, UINT_MAX);
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/* Start interruption-poll thread */
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k_thread_create(&dev_data->rx_thread, dev_data->rx_thread_stack,
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K_THREAD_STACK_SIZEOF(dev_data->rx_thread_stack),
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rx_thread, (void *) dev, NULL, NULL,
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K_PRIO_COOP(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO),
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0, K_NO_WAIT);
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HAL_ETH_DMATxDescListInit(heth, dma_tx_desc_tab,
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&dma_tx_buffer[0][0], ETH_TXBUFNB);
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HAL_ETH_DMARxDescListInit(heth, dma_rx_desc_tab,
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&dma_rx_buffer[0][0], ETH_RXBUFNB);
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HAL_ETH_Start(heth);
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disable_mcast_filter(heth);
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LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x",
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dev_data->mac_addr[0], dev_data->mac_addr[1],
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dev_data->mac_addr[2], dev_data->mac_addr[3],
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dev_data->mac_addr[4], dev_data->mac_addr[5]);
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/* Register Ethernet MAC Address with the upper layer */
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net_if_set_link_addr(iface, dev_data->mac_addr,
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sizeof(dev_data->mac_addr),
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NET_LINK_ETHERNET);
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ethernet_init(iface);
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}
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static enum ethernet_hw_caps eth_stm32_hal_get_capabilities(struct device *dev)
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{
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ARG_UNUSED(dev);
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return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T;
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}
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static const struct ethernet_api eth_api = {
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.iface_api.init = eth_iface_init,
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.get_capabilities = eth_stm32_hal_get_capabilities,
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.send = eth_tx,
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};
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static struct device DEVICE_NAME_GET(eth0_stm32_hal);
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static void eth0_irq_config(void)
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{
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IRQ_CONNECT(ETH_IRQn, CONFIG_ETH_STM32_HAL_IRQ_PRI, eth_isr,
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DEVICE_GET(eth0_stm32_hal), 0);
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irq_enable(ETH_IRQn);
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}
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static const struct eth_stm32_hal_dev_cfg eth0_config = {
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.config_func = eth0_irq_config,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMAC },
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.pclken_tx = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACTX },
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.pclken_rx = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACRX },
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.pclken_ptp = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACPTP },
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};
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static struct eth_stm32_hal_dev_data eth0_data = {
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.heth = {
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.Instance = ETH,
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.Init = {
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.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE,
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.PhyAddress = CONFIG_ETH_STM32_HAL_PHY_ADDRESS,
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.RxMode = ETH_RXINTERRUPT_MODE,
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.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE,
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#if defined(CONFIG_ETH_STM32_HAL_MII)
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.MediaInterface = ETH_MEDIA_INTERFACE_MII,
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#else
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.MediaInterface = ETH_MEDIA_INTERFACE_RMII,
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#endif
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},
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},
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.mac_addr = {
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/* ST's OUI */
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0x00,
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0x80,
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0xE1,
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#if !defined(CONFIG_ETH_STM32_HAL_RANDOM_MAC)
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CONFIG_ETH_STM32_HAL_MAC3,
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CONFIG_ETH_STM32_HAL_MAC4,
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CONFIG_ETH_STM32_HAL_MAC5
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#endif
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},
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};
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NET_DEVICE_INIT(eth0_stm32_hal, CONFIG_ETH_STM32_HAL_NAME, eth_initialize,
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ð0_data, ð0_config, CONFIG_ETH_INIT_PRIORITY, ð_api,
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ETHERNET_L2, NET_L2_GET_CTX_TYPE(ETHERNET_L2), ETH_STM32_HAL_MTU);
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