182 lines
5.3 KiB
C
182 lines
5.3 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_EDAC_IBECC_H_
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#define ZEPHYR_DRIVERS_EDAC_IBECC_H_
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/* TODO: Add to include/sys/util.h */
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#define BITFIELD(val, h, l) (((val) & GENMASK(h, l)) >> l)
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#define PCI_VENDOR_ID_INTEL 0x8086
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/* Supported SKU map */
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#define PCI_DEVICE_ID_SKU5 0x4514
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#define PCI_DEVICE_ID_SKU6 0x4528
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#define PCI_DEVICE_ID_SKU7 0x452a
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#define PCI_DEVICE_ID_SKU8 0x4516
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#define PCI_DEVICE_ID_SKU9 0x452c
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#define PCI_DEVICE_ID_SKU10 0x452e
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#define PCI_DEVICE_ID_SKU11 0x4532
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#define PCI_DEVICE_ID_SKU12 0x4518
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#define PCI_DEVICE_ID_SKU13 0x451a
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#define PCI_DEVICE_ID_SKU14 0x4534
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#define PCI_DEVICE_ID_SKU15 0x4536
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/* TODO: Move to correct place NMI registers */
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/* NMI Status and Control Register (NMI_STS_CNT) */
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#define NMI_STS_CNT_REG 0x61
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/* Set by any source of PCH SERR (SERR_NMI_STS) */
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#define NMI_STS_SRC_SERR BIT(7)
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/* Mask for all source bits in the NMI_STS_CNT_REG */
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#define NMI_STS_SRC_MASK GENMASK(7, 6)
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/**
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* Writing 1 SERR NMI are disabled and cleared, writing 0
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* SERR NMIs are enabled
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*/
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#define NMI_STS_SERR_EN BIT(2)
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/* Mask for all enable bits in the NMI_STS_CNT_REG */
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#define NMI_STS_MASK_EN GENMASK(3, 0)
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/**
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* In-Band Error Correction Code (IBECC) protects data at a cache line
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* granularity (64 Bytes) with 16 bits SECDED code.
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* Reports following fields:
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* - CMI (Converged Memory Interface) Address
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* - Syndrome
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* - Error Type (Correctable, Uncorrectable)
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*/
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/**
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* PCI Configuration space registers area
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*/
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/* Top of Upper Usable DRAM, offset 0xa8, 64 bit */
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#define TOUUD_REG 0x2a
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#define TOUUD_MASK GENMASK(38, 20)
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/* Top of Low Usable DRAM, offset 0xbc, 32 bit */
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#define TOLUD_REG 0x2f
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#define TOLUD_MASK GENMASK(31, 20)
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/* Total amount of physical memory, offset 0xa0, 64 bit */
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#define TOM_REG 0x28
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#define TOM_MASK GENMASK(38, 20)
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/* Base address for the Host Memory Mapped Configuration space,
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* offset 0x48, 64 bit
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*/
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#define MCHBAR_REG 0x12
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#define MCHBAR_MASK GENMASK(38, 16)
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#define MCHBAR_ENABLE BIT(0)
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/* Size of Host Memory Mapped Configuration space (64K) */
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#define MCH_SIZE 0x10000
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/* Capability register, offset 0xec, 32 bit */
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#define CAPID0_C_REG 0x3b
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#define CAPID0_C_IBECC_ENABLED BIT(15)
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/* Register controlling reporting error SERR, offset 0xc8, 16 bit */
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#define ERRSTS_REG 0x32
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#define ERRSTS_IBECC_COR BIT(6) /* Correctable error */
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#define ERRSTS_IBECC_UC BIT(7) /* Uncorrectable error */
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/* Register controlling Host Bridge responses to system errors,
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* offset 0xca, 16 bit
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*
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* TODO: Fix this after PCI access is fixed, now we have to access
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* ERRSTS_REG with 32 bit access and get this 16 bits
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*/
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#define ERRCMD_REG 0x32
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#define ERRCMD_IBECC_COR BIT(6) /* Correctable error */
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#define ERRCMD_IBECC_UC BIT(7) /* Uncorrectable error */
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/**
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* Host Memory Mapped Configuration Space (MCHBAR) registers area
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*/
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#define CHANNEL_HASH 0x5024
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/* ECC Injection Registers */
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#define IBECC_INJ_ADDR_BASE 0xdd88
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#define INJ_ADDR_BASE_MASK GENMASK(38, 6)
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#define IBECC_INJ_ADDR_MASK 0xdd80
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#define INJ_ADDR_BASE_MASK_MASK GENMASK(38, 6)
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#define IBECC_INJ_ADDR_CTRL 0xdd98
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#define INJ_CTRL_COR 0x1
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#define INJ_CTRL_UC 0x5
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/* Error Logging Registers */
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/* ECC Error Log register, 64 bit (ECC_ERROR_LOG) */
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#define IBECC_ECC_ERROR_LOG 0xdd70
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/* Uncorrectable (Multiple-bit) Error Status (MERRSTS) */
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#define ECC_ERROR_MERRSTS BIT64(63)
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/* Correctable Error Status (CERRSTS) */
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#define ECC_ERROR_CERRSTS BIT64(62)
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#define ECC_ERROR_ERRTYPE(val) BITFIELD(val, 63, 62)
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/* CMI address of the address block of main memory where error happened */
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#define ECC_ERROR_ERRADD(val) ((val) & GENMASK(38, 5))
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/* ECC Error Syndrome (ERRSYND) */
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#define ECC_ERROR_ERRSYND(val) BITFIELD(val, 61, 46)
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/* Parity Error Log (PARITY_ERR_LOG) */
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#define IBECC_PARITY_ERROR_LOG 0xdd78
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/* Error Status (ERRSTS) */
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#define PARITY_ERROR_ERRSTS BIT64(63)
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/* Memory configuration registers */
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#define DRAM_MAX_CHANNELS 2
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#define DRAM_MAX_DIMMS 2
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/* Memory channel decoding register, 32 bit */
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#define MAD_INTER_CHAN 0x5000
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#define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0)
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/* Enhanced channel mode for LPDDR4 */
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#define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3)
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/* Channel L mapping to physical channel */
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#define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4)
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/* Channel S size in multiples of 0.5GB */
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#define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12)
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/* DRAM decode stage 2 registers, 32 bit */
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#define MAD_INTRA_CH(index) (0x5004 + index * sizeof(uint32_t))
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/* Virtual DIMM L mapping to physical DIMM */
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#define DIMM_L_MAP(v) BITFIELD(v, 0, 0)
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/* DIMM channel characteristic 2 registers, 32 bit */
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#define MAD_DIMM_CH(index) (0x500c + index * sizeof(uint32_t))
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/* Size of DIMM L in 0.5GB multiples */
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#define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29)
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/* DIMM L width of DDR chips (DLW) */
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#define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7)
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/* Size of DIMM S in 0.5GB multiples */
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#define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29)
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/* DIMM S width of DDR chips (DSW) */
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#define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24)
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/* MC Channel Selection register, 32 bit */
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#define CHANNEL_HASH 0x5024
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/* MC Enhanced Channel Selection register, 32 bit */
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#define CHANNEL_EHASH 0x5028
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struct ibecc_error {
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uint32_t type;
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uint64_t address;
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uint16_t syndrome;
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};
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#define PCI_HOST_BRIDGE PCIE_BDF(0, 0, 0)
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#endif /* ZEPHYR_DRIVERS_EDAC_IBECC_H_ */
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