209 lines
6.1 KiB
C
209 lines
6.1 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/pinmux.h>
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#include <soc.h>
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static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
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(MCHP_GPIO_PORT_A_BITMAP),
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(MCHP_GPIO_PORT_B_BITMAP),
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(MCHP_GPIO_PORT_C_BITMAP),
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(MCHP_GPIO_PORT_D_BITMAP),
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(MCHP_GPIO_PORT_E_BITMAP),
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(MCHP_GPIO_PORT_F_BITMAP)
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};
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struct pinmux_xec_config {
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__IO uint32_t *pcr1_base;
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uint32_t port_num;
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};
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static int pinmux_xec_set(const struct device *dev, uint32_t pin,
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uint32_t func)
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{
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const struct pinmux_xec_config *config = dev->config;
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__IO uint32_t *current_pcr1;
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uint32_t pcr1 = 0;
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uint32_t mask = 0;
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/* Validate pin number in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0) {
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return -EINVAL;
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}
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mask |= MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_MUX_MASK;
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/* Check for open drain/push_pull setting */
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if (func & MCHP_GPIO_CTRL_BUFT_OPENDRAIN) {
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pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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} else {
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pcr1 |= MCHP_GPIO_CTRL_BUFT_PUSHPULL;
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}
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/* Parse mux mode */
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pcr1 |= func & MCHP_GPIO_CTRL_MUX_MASK;
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/* Figure out the pullup/pulldown configuration */
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mask |= MCHP_GPIO_CTRL_PUD_MASK;
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if (func & MCHP_GPIO_CTRL_PUD_PU) {
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/* Enable the pull and select the pullup resistor. */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
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} else if (func & MCHP_GPIO_CTRL_PUD_PD) {
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/* Enable the pull and select the pulldown resistor */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
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} else {
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/* None : Pin tristates when no active driver is present
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* on the pin. This is the POR setting
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*/
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pcr1 |= MCHP_GPIO_CTRL_PUD_NONE;
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}
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/* Make sure gpio isrs are disabled */
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pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
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mask |= MCHP_GPIO_CTRL_IDET_MASK;
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/* Now write contents of pcr1 variable to the PCR1 register that
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* corresponds to the pin configured
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*/
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current_pcr1 = config->pcr1_base + pin;
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*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
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return 0;
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}
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static int pinmux_xec_get(const struct device *dev, uint32_t pin,
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uint32_t *func)
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{
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const struct pinmux_xec_config *config = dev->config;
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__IO uint32_t *current_pcr1;
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/* Validate pin number in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0) {
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return -EINVAL;
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}
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current_pcr1 = config->pcr1_base + pin;
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*func = *current_pcr1 & (MCHP_GPIO_CTRL_BUFT_MASK
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| MCHP_GPIO_CTRL_MUX_MASK
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| MCHP_GPIO_CTRL_PUD_MASK);
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return 0;
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}
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static int pinmux_xec_pullup(const struct device *dev, uint32_t pin,
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uint8_t func)
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{
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return -ENOTSUP;
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}
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static int pinmux_xec_input(const struct device *dev, uint32_t pin,
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uint8_t func)
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{
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return -ENOTSUP;
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}
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static int pinmux_xec_init(const struct device *dev)
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{
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/* Nothing to do. The PCR clock is enabled at reset. */
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return 0;
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}
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static const struct pinmux_driver_api pinmux_xec_driver_api = {
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.set = pinmux_xec_set,
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.get = pinmux_xec_get,
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.pullup = pinmux_xec_pullup,
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.input = pinmux_xec_input,
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};
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#define PINMUX_ADDR(n) DT_REG_ADDR(DT_PHANDLE(DT_NODELABEL(n), ph_reg))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_000_036), okay)
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static const struct pinmux_xec_config pinmux_xec_port000_036_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_000_036),
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.port_num = MCHP_GPIO_000_036,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_000_036),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port000_036_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_000_036), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_040_076), okay)
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static const struct pinmux_xec_config pinmux_xec_port040_076_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_040_076),
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.port_num = MCHP_GPIO_040_076,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_040_076),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port040_076_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_040_076), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_100_136), okay)
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static const struct pinmux_xec_config pinmux_xec_port100_136_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_100_136),
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.port_num = MCHP_GPIO_100_136,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_100_136),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port100_136_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_100_136), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_140_176), okay)
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static const struct pinmux_xec_config pinmux_xec_port140_176_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_140_176),
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.port_num = MCHP_GPIO_140_176,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_140_176),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port140_176_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_140_176), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_200_236), okay)
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static const struct pinmux_xec_config pinmux_xec_port200_236_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_200_236),
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.port_num = MCHP_GPIO_200_236,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_200_236),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port200_236_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_200_236), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_240_276), okay)
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static const struct pinmux_xec_config pinmux_xec_port240_276_config = {
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.pcr1_base = (uint32_t *) PINMUX_ADDR(pinmux_240_276),
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.port_num = MCHP_GPIO_240_276,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(pinmux_240_276),
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&pinmux_xec_init,
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device_pm_control_nop,
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NULL, &pinmux_xec_port240_276_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&pinmux_xec_driver_api);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_240_276), okay) */
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