109 lines
1.8 KiB
Plaintext
109 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases{
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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mailbox-0 = &mailbox0;
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spi-5 = &spi5;
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usart-0 = &usart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-m0+";
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reg = <1>;
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};
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};
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sram0:memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x10000>;
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};
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sram1:memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 0x10000>;
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};
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sram2:memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 0x8000>;
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};
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sramx:memory@40000000{
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compatible = "mmio-sram";
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reg = <0x40000000 0x8000>;
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};
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soc {
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flash0:flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 0x40000>;
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};
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usart0:usart@40086000 {
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compatible = "nxp,lpc-usart";
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reg = <0x40086000 0xE44>;
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interrupts = <14 0>;
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label = "USART_0";
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status = "disabled";
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};
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gpio0: gpio@0 {
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compatible = "nxp,lpc-gpio";
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reg = <0x4008c000 0x2488>;
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interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,lpc-gpio";
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reg = <0x4008C000 0x2488>;
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interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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mailbox0:mailbox@4008b000 {
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compatible = "nxp,lpc-mailbox";
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reg = <0x4008b000 0xEC>;
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interrupts = <31 0>;
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label = "MAILBOX_0";
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status = "disabled";
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};
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spi5: spi@40096000 {
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compatible = "nxp,lpc-spi";
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reg = <0x40096000 0x1000>;
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interrupts = <19 0>;
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label = "SPI_5";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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