220 lines
5.3 KiB
Plaintext
220 lines
5.3 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "SiFive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
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model = "SiFive,FE310G-0002-Z0";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&modeselect &maskrom &otp &spi0>;
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reg = <0>;
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riscv,isa = "rv32imac";
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sifive,dtim = <&dtim>;
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sifive,itim = <&itim>;
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status = "okay";
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timebase-frequency = <32768>;
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hlic: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "SiFive,FE310G-0002-Z0-soc", "fe310-soc",
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"sifive-soc", "simple-bus";
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ranges;
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aon: aon@10000000 {
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compatible = "sifive,aon0";
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interrupt-parent = <&plic>;
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interrupts = <1 2>;
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reg = <0x10000000 0x1000>;
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reg-names = "control";
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};
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clint: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&hlic 3 &hlic 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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debug: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&hlic 65535>;
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reg = <0x0 0x1000>;
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reg-names = "control";
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};
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dtim: dtim@80000000 {
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compatible = "sifive,dtim0";
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reg = <0x80000000 0x4000>;
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reg-names = "mem";
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};
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error-device@3000 {
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compatible = "sifive,error0";
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reg = <0x3000 0x1000>;
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reg-names = "mem";
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};
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gpio0: gpio@10012000 {
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compatible = "sifive,gpio0";
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gpio-controller;
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interrupt-parent = <&plic>;
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interrupts = <8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
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26 27 28 29 30 31 32 33 34 35 36 37 38 39>;
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reg = <0x10012000 0x1000>;
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reg-names = "control";
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label = "gpio_0";
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status = "disabled";
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#gpio-cells = <2>;
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};
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i2c0: i2c@10016000 {
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compatible = "sifive,i2c0";
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interrupt-parent = <&plic>;
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interrupts = <52>;
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reg = <0x10016000 0x1000>;
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reg-names = "control";
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label = "i2c_0";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0";
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0xc000000 0x2000
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0xc002000 0x1fe000
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0xc200000 0x2000000>;
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reg-names = "prio", "irq_en", "reg";
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riscv,max-priority = <7>;
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riscv,ndev = <52>;
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};
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itim: itim@8000000 {
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compatible = "sifive,itim0";
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reg = <0x8000000 0x4000>;
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reg-names = "mem";
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};
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otp: otp@10010000 {
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compatible = "sifive,otp0";
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reg = <0x10010000 0x1000 0x20000 0x2000>;
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reg-names = "control", "mem";
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};
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prci: prci@10008000 {
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compatible = "sifive,freedome300prci0";
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reg = <0x10008000 0x1000>;
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reg-names = "control";
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};
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pwm0: pwm@10015000 {
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compatible = "sifive,pwm0";
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interrupt-parent = <&plic>;
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interrupts = <40 41 42 43>;
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reg = <0x10015000 0x1000>;
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reg-names = "control";
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label = "pwm_0";
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status = "disabled";
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sifive,compare-width = <8>;
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#pwm-cells = <2>;
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};
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pwm1: pwm@10025000 {
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compatible = "sifive,pwm0";
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interrupt-parent = <&plic>;
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interrupts = <44 45 46 47>;
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reg = <0x10025000 0x1000>;
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reg-names = "control";
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label = "pwm_1";
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status = "disabled";
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sifive,compare-width = <16>;
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#pwm-cells = <2>;
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};
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pwm2: pwm@10035000 {
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compatible = "sifive,pwm0";
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interrupt-parent = <&plic>;
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interrupts = <48 49 50 51>;
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reg = <0x10035000 0x1000>;
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reg-names = "control";
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label = "pwm_2";
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status = "disabled";
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sifive,compare-width = <16>;
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#pwm-cells = <2>;
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};
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modeselect: rom@1000 {
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compatible = "sifive,modeselect0";
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reg = <0x1000 0x1000>;
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reg-names = "mem";
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};
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maskrom: rom@10000 {
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compatible = "sifive,maskrom0";
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reg = <0x10000 0x2000>;
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reg-names = "mem";
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};
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uart0: serial@10013000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <3>;
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reg = <0x10013000 0x1000>;
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reg-names = "control";
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label = "uart_0";
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status = "disabled";
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};
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uart1: serial@10023000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <4>;
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reg = <0x10023000 0x1000>;
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reg-names = "control";
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label = "uart_1";
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status = "disabled";
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};
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spi0: spi@10014000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <5>;
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reg = <0x10014000 0x1000 0x20000000 0x20000000>;
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reg-names = "control", "mem";
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label = "spi_0";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@10024000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <6>;
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reg = <0x10024000 0x1000>;
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reg-names = "control";
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label = "spi_1";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@10034000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <7>;
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reg = <0x10034000 0x1000>;
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reg-names = "control";
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label = "spi_2";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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teststatus: teststatus@4000 {
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compatible = "sifive,test0";
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reg = <0x4000 0x1000>;
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reg-names = "control";
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};
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};
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};
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