89 lines
1.5 KiB
Plaintext
89 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-m33";
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reg = <1>;
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};
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};
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sram0:memory@30000000 {
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compatible = "mmio-sram";
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reg = <0x30000000 DT_SIZE_K(64)>;
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};
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sram1:memory@30010000 {
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compatible = "mmio-sram";
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reg = <0x30010000 DT_SIZE_K(64)>;
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};
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sram2:memory@30020000 {
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compatible = "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(64)>;
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};
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sram3:memory@30030000 {
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compatible = "mmio-sram";
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reg = <0x30030000 DT_SIZE_K(64)>;
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};
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sramx:memory@14000000{
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compatible = "mmio-sram";
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reg = <0x14000000 DT_SIZE_K(32)>;
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};
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soc {
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flash0:flash@10000000 {
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compatible = "soc-nv-flash";
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reg = <0x10000000 DT_SIZE_K(630)>;
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};
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usart0:usart@50086000 {
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compatible = "nxp,lpc-usart";
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reg = <0x50086000 0xE44>;
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interrupts = <14 0>;
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label = "USART_0";
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status = "disabled";
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};
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gpio0: gpio@0 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x5008c000 0x2488>;
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interrupts = <2 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x5008c000 0x2488>;
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interrupts = <3 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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