55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/*
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* Copyright (c) 2021, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief GPIO macros for the Elkhart Lake SoC
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*
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* This header file is used to specify the GPIO macros for
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* the ELkhart Lake SoC.
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*/
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#ifndef __SOC_GPIO_H_
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#define __SOC_GPIO_H_
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#define GPIO_INTEL_NR_SUBDEVS 15
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#define REG_PAD_OWNER_BASE 0x0020
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#define REG_GPI_INT_STS_BASE 0x0100
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#define PAD_CFG0_PMODE_MASK (0x0F << 10)
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#define REG_PAD_BASE_ADDR 0x000C
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#define REG_GPI_INT_EN_BASE 0x0120
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#define REG_PAD_HOST_SW_OWNER 0x0B0
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#define PAD_BASE_ADDR_MASK 0xfff
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#define GPIO_REG_BASE(reg_base) \
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(reg_base & ~PAD_BASE_ADDR_MASK)
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#define GPIO_PAD_BASE(reg_base) \
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(reg_base & PAD_BASE_ADDR_MASK)
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#define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset) \
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(pin_offset % 8) ? \
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REG_PAD_OWNER_BASE + \
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((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
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REG_PAD_OWNER_BASE + \
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(((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
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#define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
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#define GPIO_RAW_PIN(pin, pin_offset) pin
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#define GPIO_INTERRUPT_BASE(cfg) \
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(cfg->group_index * 0x4)
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#define GPIO_BASE(cfg) \
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(cfg->group_index * 0x4)
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#define PIN_OFFSET 0x10
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#endif /* __SOC_GPIO_H_ */
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