104 lines
2.4 KiB
Plaintext
104 lines
2.4 KiB
Plaintext
/*
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* Copyright (c) 2023 Rahul Arasikere
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f7/stm32f7.dtsi>
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/ {
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/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
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* 16KB SRAM2 @ 2007C000
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*/
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sram0: memory@20020000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(384)>;
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zephyr,memory-region = "SRAM0";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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soc {
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compatible = "st,stm32f765", "st,stm32f7", "simple-bus";
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pinctrl: pin-controller@40020000 {
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reg = <0x40020000 0x2C00>;
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gpioj: gpio@40022400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
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};
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gpiok: gpio@40022800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
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};
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};
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i2c4: i2c@40006000 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40006000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
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interrupts = <95 0>, <96 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi6: spi@40015400 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
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interrupts = <86 5>;
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status = "disabled";
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};
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mac: ethernet@40028000 {
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compatible = "st,stm32-ethernet";
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reg = <0x40028000 0x8000>;
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interrupts = <61 0>;
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clock-names = "stmmaceth", "mac-clk-tx",
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"mac-clk-rx", "mac-clk-ptp";
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
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<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
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<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
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<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
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status = "disabled";
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};
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sdmmc2: sdmmc@40011c00 {
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compatible = "st,stm32-sdmmc";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
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<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
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resets = <&rctl STM32_RESET(APB2, 7U)>;
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interrupts = <103 0>;
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status = "disabled";
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};
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};
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smbus4: smbus4 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c4>;
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status = "disabled";
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};
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};
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